[libre-riscv-dev] daily kan-ban update 20jul2020

[Cesar Strauss <cestrauss@gmail.com>]

Yesterday:

* Finished an example of a FSM-based Shifter:
src/soc/experiment/alu_fsm.py
https://bugs.libre-soc.org/show_bug.cgi?id=417

* Started investigating a difference in simulation results between pysim
and cxxsim, with regards to the Shifter example.
It was established that cxxsim probably has a bug.
https://github.com/nmigen/nmigen/issues/439

Today:

* Continue investigating the potential bug in cxxsim.
I think the test case can be simplified by taking out the SHIFT state
and keeping just the handshake states (IDLE and DONE). This would imply,
in turn, that a one bit register should be enough to trigger the problem.
Will add my findings to nMigen #439.

* Fix alu_fsm.py to work in pysim again.

Next:

* Shave an extra cycle from the Shifter, by short-circuiting IDLE and
going straight to SHIFT, when valid_i is already high at DONE. Most
likely, will do it in a new Shifter, to keep this one as simple as possible.

* Thinking about implementing an almost-free exponential speedup, by
shifting by 1,2,4,.. in sequence.

* Simplify my half-finished parallel test case in
src/soc/experiment/test/test_compalu_multi.py, which is too detailed.
Just test for functionality, leave correctness to formal proofs.

* Investigate the possibility to generate useful, structured, commented,
color-formatted gtkw templates in test cases, using the vcd.gtkw module
from pyvcd (which is already a dependency of nMigen).

Cesar

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