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From: Cole Poirier <colepoirier@gmail.com>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Cc: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] daily kan-ban update 26may2020
Date: Tue, 26 May 2020 11:00:19 -0700
Message-ID: <3F54AFB8-8C2A-48D9-8473-31441A492780@getmailspring.com> (raw)
In-Reply-To: <CAPweEDyiaZJgHt5Ow1prbNMQs_Tk3TijiS6oiNDhqBDGH+tjxA@mail.gmail.com>

On May 26 2020, at 10:35 am, Luke Kenneth Casson Leighton
<lkcl@lkcl.net> wrote: 
> i have a feeling we just call RegFileArray.read_port() and write_port,
> then not let anyone access the 8 reg-ports, throw away the "global"
> thing and create the alternative one.

Having done a close read of regfile/virtual_port.py (apologies for
giving a "terrible name for a complex register"), and reviewing the
yosys show top logic diagram I think I mostly understand what's going on
in this module.

Regarding the "global" thing, are you referring to the self.wr/rd_ports
"for external use"? We should instead just use the existing methods on
RegFileArray to set up the external ports? How do we go about not
letting anyone access the 8 reg-ports?

Cole

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Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-26 14:40 Luke Kenneth Casson Leighton
2020-05-26 16:44 ` Cesar Strauss
2020-05-26 17:07   ` Luke Kenneth Casson Leighton
2020-05-26 16:47 ` Michael Nolan
2020-05-26 17:02   ` Cole Poirier
2020-05-26 17:24     ` Luke Kenneth Casson Leighton
2020-05-26 17:29       ` Cole Poirier
2020-05-26 17:35         ` Luke Kenneth Casson Leighton
2020-05-26 18:00           ` Cole Poirier [this message]
2020-05-26 19:46             ` Luke Kenneth Casson Leighton
2020-05-26 17:08   ` Luke Kenneth Casson Leighton
2020-05-26 17:49   ` Luke Kenneth Casson Leighton
2020-05-26 17:57     ` Michael Nolan
2020-05-26 19:13 ` Jacob Lifshay
2020-05-26 19:51   ` Luke Kenneth Casson Leighton
2020-05-26 19:54 ` Tobias Platen
2020-05-26 20:00   ` Luke Kenneth Casson Leighton

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