Re: [libre-riscv-dev] daily kan-ban update 11jun2020

[Cesar Strauss <cestrauss@gmail.com>]

Ongoing:

* Work on the parallel test concept in
src/soc/experiment/test/test_compalu_multi.py.

Recently:

* Implement proper ready / valid signaling on the test ALU at
src/soc/experiment/alu_hier.py

Today:

* Looking into compldst_multi.py's unit tests to confirm that they are
properly functional
* (off-project): git bisecting systemd due to getting system freezes
after an upgrade. Fun.

Interesting tools and readings, to share:

* Pipelined Skid Buffer

http://fpgacpu.ca/fpga/Pipeline_Skid_Buffer.html

The circuit itself is useful, for meeting timing on long pipelines. But,
specially, I find it a nice example of the Finite State Machine (FSM)
technique, from requirements, concept and diagram, to design and
implementation. Doesn't cover unit tests and formal proofs, though.

* GTKWave package, from the PyVCD module

https://pyvcd.readthedocs.io/en/latest/vcd.gtkw.html

While used in a limited way by nMigen itself, for pre-filling traces in
a GTKWave window, it can do much more: comments, blank separators, trace
colors, scale, etc.

* Synchronous Resets? Asynchronous Resets? I am so confused! How will I
ever know which to use? by Clifford E. Cummings

http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_Resets.pdf

* Clock Domain Crossing (CDC) Design & Verification Techniques Using
SystemVerilog, by Clifford E. Cummings

http://www.sunburst-design.com/papers/CummingsSNUG2008Boston_CDC.pdf

In particular, see section 5.8.2: Multi-bit CDC signal passing using
1-deep / 2-register FIFO synchronizer.

* Understanding Latency Hiding on GPUs, by Vasily Volkov

http://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-143.pdf

Nice introductory chapter on internal GPU architecture.

Regards,

Cesar

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