From: "Immanuel, Yehowshua U" <yimmanuel3@gatech.edu>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] submitted bugreport to upstream nmigen
Date: Thu, 2 Apr 2020 18:19:07 +0000
Message-ID: <990AC263-E280-4086-BBE8-6612B527736A@gatech.edu> (raw)
In-Reply-To: <CAPweEDyftS_SXb6Za4Oa6Ubs+Eg9C-3V0+ZvGVYtUhVukpmEiQ@mail.gmail.com>
> fantastic to hear that. must contact her and offer some € for nmigen
> work. in particular we need simulation of SR NAND latch and support
> for it to output into yosys.
Yes. Whitequark is great. I had contacted ‘quark some time ago about supporting her work directly.
It would be nice if we could support her work on YosysCXX too.
Yehowshua
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Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-01 3:21 Jacob Lifshay
2020-04-01 10:16 ` Luke Kenneth Casson Leighton
2020-04-02 3:03 ` Jacob Lifshay
2020-04-02 9:27 ` Luke Kenneth Casson Leighton
2020-04-02 18:19 ` Immanuel, Yehowshua U [this message]
2020-04-03 4:10 ` Jacob Lifshay
2020-04-03 10:37 ` Luke Kenneth Casson Leighton
2020-04-03 17:41 ` Jacob Lifshay
2020-04-03 18:11 ` Luke Kenneth Casson Leighton
2020-04-03 18:26 ` Jacob Lifshay
2020-04-03 19:24 ` Luke Kenneth Casson Leighton
2020-04-03 20:21 ` Jacob Lifshay
2020-04-03 21:48 ` Luke Kenneth Casson Leighton
2020-04-04 8:15 ` Frieder Paape
2020-04-04 11:07 ` Luke Kenneth Casson Leighton
2020-04-03 20:27 ` Cole Poirier
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