From: Cole Poirier <colepoirier@gmail.com>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Cc: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] daily kan-ban update 01jun2020
Date: Tue, 2 Jun 2020 15:48:26 -0700
Message-ID: <9D360AEA-C7A4-41EC-B9CA-DCEBF39E6F40@getmailspring.com> (raw)
In-Reply-To: <CAPweEDyFts_=98SQUJQ2HQj99sOBTsF69O0DWCP3MrRDyFn8Xg@mail.gmail.com>
On Jun 2 2020, at 3:11 am, Luke Kenneth Casson Leighton <lkcl@lkcl.net> wrote:
> On Tue, Jun 2, 2020 at 1:23 AM Cole Poirier <colepoirier@gmail.com> wrote:
>>
>> Today (actual):
>>
>> Spent today reading the parts of OPENPOWER ISA v3.1 related to traps,
>> not finished yet. I don't understand very much currently, but I think
>> that this will progress as I read and investigate further, however,
>> since I don't think I can read the spec well enough to understand
>> what I
>> have to implement for fu/trap/main_stage, if someone else has the
>> time I
>> think they should do it. Otherwise, I'll continue to work away at
>> understanding enough of the spec to be able to implement the trap pipeline.
>
> it is not in the least bit necessary to "understand" the spec. i do not.
>
> what *is* necessary is to understand how to translate microwatt VHDL
> source code into nmigen.
>
> and to TRUST that microwatt is correct.
>
> this is why i have put in code-snippets from microwatt into the bugreport.
>
> this turns an exercise that would take months if not years by a factor
> of approximately TEN.
>
> quotes understanding quotes comes later.
>
> l.
Aha! Thanks for this course correction Luke. I reviewed the comments on
the bug report yesterday, but I will now review it again with this fresh
knowledge, and get to work translating the microwatt VHDL into nmigen
for the trap pipeline.
Cole
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Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-01 10:40 Luke Kenneth Casson Leighton
2020-06-01 16:20 ` Tobias Platen
2020-06-01 18:30 ` Cole Poirier
2020-06-01 18:33 ` Luke Kenneth Casson Leighton
2020-06-01 19:03 ` Cole Poirier
2020-06-01 19:05 ` Luke Kenneth Casson Leighton
2020-06-02 0:22 ` Cole Poirier
2020-06-02 10:11 ` Luke Kenneth Casson Leighton
2020-06-02 22:48 ` Cole Poirier [this message]
2020-06-02 23:03 ` Luke Kenneth Casson Leighton
2020-06-02 23:05 ` Cole Poirier
2020-06-01 18:54 ` Michael Nolan
2020-06-01 19:02 ` Luke Kenneth Casson Leighton
2020-06-02 6:17 ` Jacob Lifshay
2020-06-02 10:18 ` Luke Kenneth Casson Leighton
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