[libre-riscv-dev] Handling Interrupts

From: Yehowshua <yimmanuel3@gatech.edu>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: [libre-riscv-dev] Handling Interrupts
Date: Sat, 9 May 2020 13:23:58 -0400
Message-ID: <BF4B573A-FB3D-48E0-9AFD-9921CC8F01C1@gatech.edu> (raw)

One thing I just realized that I’ve never done in any of the RTL CPUs I’ve worked with is enable interrupts.

How are interrupts done in RTL? As soon as the CPU controller sees that EINT is high, does it(upon the next clock boundary), flush the pipeline and immediately jump to the handler?

I’m aware that there can be external hardware such as a PLIC to arbitrate interrupts, I’m just not certain about the actual CPU RTL - what it would do. That is, if the CPU immediately jumps to the handler address - or if it bothers to save a few register first( this might depend on the actual ISA itself too).

I see that for MIPS(link below), there is a dedicated area in memory to dump the current GPR values.

https://courses.engr.illinois.edu/cs232/sp2012/section/disc5.pdf <https://courses.engr.illinois.edu/cs232/sp2012/section/disc5.pdf>

Yehowshua
_______________________________________________
libre-riscv-dev mailing list
libre-riscv-dev@lists.libre-riscv.org
http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev