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From: Jacob Lifshay <programmerjake@gmail.com>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] [Bug 258] Finish implementing support for Power in simple-soft-float
Date: Wed, 18 Mar 2020 00:02:22 -0700
Message-ID: <CAC2bXD7K16c0o6RCXcJGYq2V6=_HordVPe5gmWVOYwko1BoM2A@mail.gmail.com> (raw)
In-Reply-To: <CAPweEDz1e-RXfd8-dD6Q4QPPQfcVNCCbJ4e8Vb1mD2ZrJVCDiw@mail.gmail.com>

On Tue, Mar 17, 2020, 23:58 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
wrote:

> On Wednesday, March 18, 2020, <bugzilla-daemon@libre-riscv.org> wrote:
>
> > http://bugs.libre-riscv.org/show_bug.cgi?id=258
> >
> > --- Comment #1 from Jacob Lifshay <programmerjake@gmail.com> ---
> > Just finished some refactoring in preparation for supporting Power's
> weird
> > FP
> > status flags.
>
>
>  the FP HDL needs a big update to bring out status bits.  then another one
> to add rounding modes, which is quite a bit of work.
>

Adding status bits and adding rounding modes should be done together,
because they are closely interrelated, especially inexact and underflow.

If you do them separately, you will only be making more work for yourself.

Jacob
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Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-15 18:02 [libre-riscv-dev] [Bug 258] New: " bugzilla-daemon
2020-03-18  4:37 ` [libre-riscv-dev] [Bug 258] " bugzilla-daemon
2020-03-18  6:57   ` Luke Kenneth Casson Leighton
2020-03-18  7:02     ` Jacob Lifshay [this message]
2020-03-23  1:24 ` bugzilla-daemon
2020-03-23  9:22 ` bugzilla-daemon
2020-03-23 10:00 ` bugzilla-daemon

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