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From: Samuel Falvo II <sam.falvo@gmail.com>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] Signal names for trap pipeline??
Date: Fri, 17 Jul 2020 19:09:39 -0700
Message-ID: <CAEz=somsR1-xOVhaMJNow2xMrchGE182dL0FScM_jtJOcUAJPw@mail.gmail.com> (raw)
In-Reply-To: <CAEz=son5eze0Hy5T_FnGO3gxMBdaAS9vG0TRvjU7-B54dgLprg@mail.gmail.com>

On Fri, Jul 17, 2020 at 5:58 PM Samuel Falvo II <sam.falvo@gmail.com> wrote:
> I'm running into an irreconcilable property violations with the formal
> properties for the trap main stage.

Please disregard; I just spotted the convenience assignments in the
TrapInputData class.  Egg, meet face.

-- 
Samuel A. Falvo II

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Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-18  0:58 Samuel Falvo II
2020-07-18  2:09 ` Samuel Falvo II [this message]
2020-07-18  2:50 ` Luke Kenneth Casson Leighton

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