[libre-riscv-dev] regfile-to-function-unit connection taking shape

[Luke Kenneth Casson Leighton <lkcl@lkcl.net>]

i put together a "non-production core" which is starting to take shape:
the first priority being to get the register file ports connected.
this involves first enumerating them, and just thinking about the data
structures involved was hampering me from making progress.

i therefore decided a while ago to drop that (after first creating the
MultiCompUnit Record system, to make it easier to come back to), and
now, after testing each MCU and being happy that they can handle
and look after their respective pipelines, it's time to connect them
to actual regfiles.

this is being done here:
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/simple/core.py;hb=HEAD

the output from that (which is for read ports only at the moment)
shows exactly what needs to be connected up.  the "lanes" designation
is purely arbitrary convenience, however the important thing is that
they are all the same "register".  lane 0 for INT is *always* RA.
lane 1 for the INT regfile is *always* RB, and so on.

the next stage will be to introduce a series of PriorityPickers,
which allow one and *only* one of the candidates (RA INT Lane 0)
access to that dedicate Regfile port.

this straight one-to-one relationship means that there is no need
for that cyclic buffer previously described.

also the plan is to very simply only allow one instruction to be
"active" at any one time (issue, wait for read, wait for busy,
wait for write, then back to issue).  this avoids the need for
any kind of Dependency Tracking, thus allowing us to actually have
"something working".

l.


-----

regfile read ports: INT
  regfile read port INT lane: 0
     alu0 ra 0:63 (<< (const 1'd1) (sig reg1)) (sig reg1_ok)
     <soc.fu.compunits.compunits.ALUFunctionUnit object at 0x7f6abac0ea58>

     cr0 ra 0:63 (<< (const 1'd1) (sig reg1)) (sig reg1_ok)
     <soc.fu.compunits.compunits.CRFunctionUnit object at 0x7f6abaa9a2b0>

     logical0 ra 0:63 (<< (const 1'd1) (sig reg1)) (sig reg1_ok)
     <soc.fu.compunits.compunits.LogicalFunctionUnit object at
0x7f6aba9984e0>

     shiftrot0 ra 0:63 (<< (const 1'd1) (sig reg1)) (sig reg1_ok)
     <soc.fu.compunits.compunits.ShiftRotFunctionUnit object at
0x7f6aba8c7ef0>

  regfile read port INT lane: 1
     alu0 rb 0:63 (<< (const 1'd1) (sig reg2)) (sig reg2_ok)
     <soc.fu.compunits.compunits.ALUFunctionUnit object at 0x7f6abac0ea58>

     cr0 rb 0:63 (<< (const 1'd1) (sig reg2)) (sig reg2_ok)
     <soc.fu.compunits.compunits.CRFunctionUnit object at 0x7f6abaa9a2b0>

     logical0 rb 0:63 (<< (const 1'd1) (sig reg2)) (sig reg2_ok)
     <soc.fu.compunits.compunits.LogicalFunctionUnit object at
0x7f6aba9984e0>

     shiftrot0 rb 0:63 (<< (const 1'd1) (sig reg2)) (sig reg2_ok)
     <soc.fu.compunits.compunits.ShiftRotFunctionUnit object at
0x7f6aba8c7ef0>

  regfile read port INT lane: 2
     shiftrot0 rc 0:63 (<< (const 1'd1) (sig reg3)) (sig reg3_ok)
     <soc.fu.compunits.compunits.ShiftRotFunctionUnit object at
0x7f6aba8c7ef0>

regfile read ports: XER
  regfile read port XER lane: 2
     alu0 xer_so 32 1 (& (slice (sig oe) 0:1) (sig oe_ok))
     <soc.fu.compunits.compunits.ALUFunctionUnit object at 0x7f6abac0ea58>

  regfile read port XER lane: 3
     alu0 xer_ca 34,45 2 (== (sig input_carry) (const 2'd2))
     <soc.fu.compunits.compunits.ALUFunctionUnit object at 0x7f6abac0ea58>

     shiftrot0 xer_ca 34,45 2 (== (sig input_carry) (const 2'd2))
     <soc.fu.compunits.compunits.ShiftRotFunctionUnit object at
0x7f6aba8c7ef0>

regfile read ports: CR
  regfile read port CR lane: 2
     cr0 full_cr 0:31 255 (sig read_cr_whole)
     <soc.fu.compunits.compunits.CRFunctionUnit object at 0x7f6abaa9a2b0>

     branch0 cr_a 0:3 (<< (const 1'd1) (sig cr_in1)) (sig cr_in1_ok)
     <soc.fu.compunits.compunits.BranchFunctionUnit object at
0x7f6abaa185c0>

  regfile read port CR lane: 3
     cr0 cr_a 0:3 (<< (const 1'd1) (sig cr_in1)) (sig cr_in1_ok)
     <soc.fu.compunits.compunits.CRFunctionUnit object at 0x7f6abaa9a2b0>

  regfile read port CR lane: 4
     cr0 cr_b 0:3 (<< (const 1'd1) (sig cr_in2)) (sig cr_in2_ok)
     <soc.fu.compunits.compunits.CRFunctionUnit object at 0x7f6abaa9a2b0>

  regfile read port CR lane: 5
     cr0 cr_c 0:3 (<< (const 1'd1) (sig cr_in2)) (sig cr_in2_ok)
     <soc.fu.compunits.compunits.CRFunctionUnit object at 0x7f6abaa9a2b0>

regfile read ports: FAST
  regfile read port FAST lane: 0
     branch0 spr1 0:63 (<< (const 1'd1) (sig fast1)) (sig fast1_ok)
     <soc.fu.compunits.compunits.BranchFunctionUnit object at
0x7f6abaa185c0>

  regfile read port FAST lane: 1
     branch0 spr2 0:63 (<< (const 1'd1) (sig fast2)) (sig fast2_ok)
     <soc.fu.compunits.compunits.BranchFunctionUnit object at
0x7f6abaa185c0>

  regfile read port FAST lane: 3
     branch0 cia 0:63 1 (const 1'd1)
     <soc.fu.compunits.compunits.BranchFunctionUnit object at
0x7f6abaa185c0>
---
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