Re: [libre-riscv-dev] daily kan-ban update 08mar2020

[Luke Kenneth Casson Leighton <lkcl@lkcl.net>]

---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

On Fri, May 8, 2020 at 9:27 PM Yehowshua <yimmanuel3@gatech.edu> wrote:
>
> Today I worked on legal things.
> Also put a rough sketch together for the minimum number of interfaces we need to support.
>
> I put USB and ethernet at second priority.

good.

> I talked with Florent from EnjoyDigital, and while LiteX supports USB, it may require some non-trivial modification on our part if we didn’t want to go with (FTDI or Cypress) chips which I think max out at 200MB/s.
>
> He pointed me to some alternatives in both Migen and nMigen:
> - https://github.com/im-tomu/valentyusb <https://github.com/im-tomu/valentyusb>
> - https://github.com/lambdaconcept/lambdaUSB <https://github.com/lambdaconcept/lambdaUSB>

right.  this one is ULPI (not USB)
https://github.com/lambdaconcept/lambdaUSB/blob/master/lambdausb/phy/ulpi.py

this one (and the corresponding rx.py) i'm not quite understanding the context
https://github.com/lambdaconcept/lambdaUSB/blob/master/lambdausb/phy/usb/tx.py


> - https://github.com/greatscottgadgets/luna <https://github.com/greatscottgadgets/luna>
>
> I’ll pop them on the Wiki.

use this:
https://libre-soc.org/shakti/m_class/USB2

or this as appropriate, depending on whether they're *actual* USB2
(which is unlikely given that it needs to be analog) or whether they
are UMTI / ULPI.
https://libre-soc.org/shakti/m_class/ULPI/ is the "parallel bus"
version - it does however need cross-referencing to the USB2 page.

i suspect that they're all ULPI... i *hope* they're not ohhh right,
FTDI.  that's almost certainly a "serial bus" (like the FT232 only a
bit faster).

basically UMTI is great (but a lot of pins), ULPI is better (needs
DDR), but *actual* USB2 (D+ and D-) requires a complex analog design.



> Litex also support ethernet which would require a $20 PHY, not great for a low cost SBC.

oink.  the RTL8192 RGMII PHY is under USD $1.  what the hell are they
doing picking a $20 PHY??

there's plenty of RGMII opencores / open cores out there, and the
litex eth looks like it supports a range:
https://github.com/enjoy-digital/liteeth/tree/master/liteeth/phy

GMII, MII, RMII but interestingly not RGMII (reduced gigabit MII).
RGMII is double-data-rate and half the bits (4 per tx, 4 per rx)

ok https://github.com/enjoy-digital/liteeth/blob/master/liteeth/phy/ecp5rgmii.py




> We could also do ethernet over USB - this would render the boot loader slightly more complex if we wished to use ethernet during the boatloader.

no, definitely not.  far too complex (booting over ethernet) and
having to initialise the USB controller as well?  no.  see dan
gisselquist's code and how much work was involved.

the typical ROM size is 8k to 16k.  that's *it*.

if you *really* have a need to boot over ethernet or over USB, it
should be done as a 2nd-stage boot chain.


> Again, ethernet is not **essential for a minimum viable ASIC.

nope it's not.

l.

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