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From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: [libre-riscv-dev] daily kan-ban update 23jul2020
Date: Thu, 23 Jul 2020 13:50:42 +0100
Message-ID: <CAPweEDwf_psXU_-e8tu_KQSw2sZFzSX_9xLHA1=nCGUZcyx2-A@mail.gmail.com> (raw)

tasks:

https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1

yestersday:

* went through trap review with samuel.  lots of improvements and bugs fixed
* talked with florian about litex integration. got "compile" but vcd is
problematic

today:

* found that running vcd2fst "fixes" gtkwave problem, allowing debugging of
LibreSOC under verilator litex sim
* started investigating 32/64 bit wishbone mismatch in litex sim

so this is a big deal: getting litex sim working is a first step to being
able to connect to a UART, which in turn will allow running the
"helloworld" and other microwatt examples properly.

next on the list will be adding support for counter SORs, then XICS and
then possibly a RADIX MMU, at which point we can run a linux kernel.

l.



-- 
---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
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Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-23 12:50 Luke Kenneth Casson Leighton [this message]
2020-07-23 12:52 ` Yehowshua
2020-07-23 16:30   ` Tobias Platen
2020-07-23 16:37     ` Luke Kenneth Casson Leighton
2020-07-23 18:26       ` Cole Poirier
2020-07-23 18:47         ` Luke Kenneth Casson Leighton
2020-07-23 19:14           ` Cole Poirier
2020-07-23 19:18             ` Jacob Lifshay
2020-07-23 19:26               ` Cole Poirier
2020-07-23 20:36                 ` Luke Kenneth Casson Leighton
2020-07-23 20:41                   ` Cole Poirier

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