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From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: [libre-riscv-dev] daily kan-ban update 07jun2020
Date: Sun, 7 Jun 2020 16:03:39 +0100
Message-ID: <CAPweEDwtHCMCtUpLp87v7Z9wg=sPi5=b7LZV+6oW4g7BbMt4EQ@mail.gmail.com> (raw)

yesterday:

* added LDSTCompUnit unit test, got it partly working for LD.  the
failures are down to L0CacheBuffer memory misalignments
* redesigned LDSTMultiCompUnit to look more like other derivatives
from MultiCompUnit
* added TestMemory to the compunit unit tests and added the ability to
initialise Simulator Memory
* went over TRAP with Cole
* discussed how to do interrupts and other exceptions (illegal
instruction) by changing the OP_xxx to OP_TRAP and executing that,
instead
* added a TRAP function (TODO) in the Simulator
* added MSR to the Simulator
* added mtmsr/mfmsr to the Simulator.

this morning/afternoon:

* tried to reduce the number of patches to auto-generated simulator
code from pseudocde (failed)
* added CA/CA32 to the parser-generator, to support sraw/srad creating
CA and CA32 in an unusual way
* updated the simulator to support the same
* updated rotator.py to match microwatt
* got the SHIFTROT unit tests working (in both fu/shift_rot
test_pipe_caller and test_shiftrot_compunit)

today:

* think about how to fix LDSTCompUnit (more specifically, the
prototype non-production L0CacheBuffer)
* continue debugging unit tests after adding CA/CA32.

l.

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