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From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: [libre-riscv-dev] idea for testing pipelines
Date: Sun, 24 May 2020 16:30:16 +0100
Message-ID: <CAPweEDx_bW16kzTa=xacG3xFqB1O98Wt=Gss9H+vQcFvpcKxpw@mail.gmail.com> (raw)

i have an idea for testing the pipelines and also the regfiles, which
could also be a (drastically simpler, brain-dead, very slow)
processor:

* to create a system which, by monitoring CompUnit "busy" signals,
only permits one pipeline at a time to be active.
* to set up some very VERY simple connectivity between CompUnits and
Regfiles, involving either a single broadcast bus or a full crossbar

that would include incrementing the PC, so as to be able to do
instruction sequences.

this would allow us to confirm the functionality of the pipelines,
without needing the Dependency Matrices, which is a big piece of HDL
and will run really slowly in simulation.

l.

---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

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