From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] daily kan-ban update 09jun2020
Date: Tue, 9 Jun 2020 21:15:39 +0100
Message-ID: <CAPweEDxcRF8mmQrGBwewE82fuhWq2G4RwrXmJmmcPOjzaWN0CQ@mail.gmail.com> (raw)
In-Reply-To: <44227E61-E658-4CBA-9ECE-CC4A193E3471@getmailspring.com>
On Tue, Jun 9, 2020 at 8:35 PM Cole Poirier <colepoirier@gmail.com> wrote:
> Today:
>
> I'm excited to start writing unit tests for the TRAP pipeline today, and
> to use the learning methodology you laid out on bug 325 for me that
> involves looking at gtkwave timing diagrams.
with michael having added the qemu-execution thing, you should now
first be able to add a "twi" (or tdi) instruction unit test to that,
first.
this will allow you to check that the *simulator* is correct.
then after you know that the *simulator* is correct, the same unit
test can be used in test_pipe_caller.py, and in that way you will then
be able to test that the *hardware* is correct.
l.
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Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-09 13:11 Luke Kenneth Casson Leighton
2020-06-09 13:23 ` Tobias Platen
2020-06-09 16:20 ` Luke Kenneth Casson Leighton
2020-06-09 17:21 ` Jacob Lifshay
2020-06-09 17:44 ` Luke Kenneth Casson Leighton
2020-06-09 19:35 ` Cole Poirier
2020-06-09 20:15 ` Luke Kenneth Casson Leighton [this message]
2020-06-09 21:01 ` Cole Poirier
2020-06-09 21:48 ` Luke Kenneth Casson Leighton
2020-06-09 22:07 ` Luke Kenneth Casson Leighton
2020-06-10 0:38 ` Cole Poirier
2020-06-10 13:16 ` Luke Kenneth Casson Leighton
2020-06-10 18:53 ` Michael Nolan
2020-06-10 21:30 ` Cole Poirier
2020-06-09 21:49 Alain D D Williams
2020-06-09 22:48 ` Luke Kenneth Casson Leighton
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