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From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: [libre-riscv-dev] daily kan-ban update 20may2020
Date: Wed, 20 May 2020 15:14:11 +0100
Message-ID: <CAPweEDxxHh-1kjXtP-ZB-u5AoGE8b1+zt6XmqVVe1fHTtw5bEA@mail.gmail.com> (raw)

yesterday:
* more pipeline stuff with michael and cole and jacob.  researched
TRAP ops in particular
* identified that MUL and DIV have similar register allocation to
SHIFT and LOGICAL
* moved MUL and DIV ops to their own respective Function Unit
(power_enums.py, csv files)
* talked with Marketnext about the resource requirements for the May
30 Hackathon.
* worked out from this image that we need to do pretty much the same thing: give
  each FunctionUnit a "consistent uniform interface" of its register
port allocation.
  https://libre-soc.org/3d_gpu/6600_scoreboard_fu_regs.png

this morning:
* created nmutil exts helper function and used it everywhere (OP_EXTS
and other places)
* helped Jean-Paul to understand the requirements for regular
coriolis2 layout of the Dep Matrices

today:

* send an agenda to Hugh, Tim, Yehowshua for the bi-weekly OpenPOWER conf call
* received a message from these guys, they would like to do a review
https://radicallyopensecurity.com/
* start putting an "API / Spec" system together for Function Units, to
be able to connect Regfiles to ports.
* do the "Record" conversion of CompALU (part of the API/Spec for FUs)

l.

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Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-20 14:14 Luke Kenneth Casson Leighton [this message]
2020-05-20 14:50 ` Cole Poirier
2020-05-20 15:14   ` Luke Kenneth Casson Leighton
2020-05-20 19:34     ` Cole Poirier
2020-05-20 19:44       ` Luke Kenneth Casson Leighton
2020-05-20 15:50 ` Michael Nolan
2020-05-20 16:23   ` Luke Kenneth Casson Leighton

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