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From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: [libre-riscv-dev] daily kan-ban update 02jun2020
Date: Tue, 2 Jun 2020 11:48:08 +0100
Message-ID: <CAPweEDy-nKkUYj-2uikQpg54GGbZW+DOhy-wcL1jBdkt3XM+xw@mail.gmail.com> (raw)

yesterday:

* got Branch CompUnit test on par with its equivalent test_pipe_caller.py
* swapped RS from position "3" to position "1" (read port 1) on all Logical ops,
  OP_EXTS, and MTCRF
* started on ShiftRot CompUnit test.  fixed bugs, discovered that sraw is
  not setting CA/CA32, discovered that "rlwinm." is not implemented.
* fixed a bug in the CompUnit testing where the source operands were not
   zero'd.  ALUs picked up and used *old* operands (from a previous instruction)
* fixed two mask-related bugs in MultiCompUnit
* started on the linking of CompUnits to regfiles, through understanding of
   the relationship between CompUnits, regspecs, and Decode2Execute1Type.

today:

* getting Decode2Execute1Type to "understand" regspecs: to provide the
  "accessor" register information in the RegSpec API, so that it becomes
  dead simple to connect Decoder, CompUnits, and Regfiles.

l.

---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

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Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-02 10:48 Luke Kenneth Casson Leighton [this message]
2020-06-02 14:44 ` Tobias Platen
2020-06-02 15:03   ` Tobias Platen
2020-06-02 15:37     ` Luke Kenneth Casson Leighton
2020-06-02 15:43       ` Tobias Platen
2020-06-02 16:04         ` Luke Kenneth Casson Leighton
2020-06-02 22:35 ` Jacob Lifshay
2020-06-02 23:02   ` Luke Kenneth Casson Leighton
2020-06-02 23:06     ` Cole Poirier
2020-06-02 23:07       ` Luke Kenneth Casson Leighton
2020-06-02 23:16         ` Luke Kenneth Casson Leighton

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