[libre-riscv-dev] tobias: note the comment here in bug #216

[Luke Kenneth Casson Leighton <lkcl@lkcl.net>]

tobias i have not seen an acknowledgement that this has been actioned:
https://bugs.libre-soc.org/show_bug.cgi?id=216

it would be much easier if you could acknowledge things. i have to
spend considerable time tracking through the git logs, monitoring them
and cut/pasting commit log messages into the bugtracker on your behalf.

with the large number of things that i am tracking, not having a response
makes it extremely difficult for me.

if you can respond and track the bugreports, and reply in them "actioned
this change as required" and so on, it cuts the amount of work that i have
to do considerably.

thanks.

l.

proof_datamerger.py:

                for b in range(0,8):

just range(8).  there is no need to specify a start range of 0

            comb += dut.addr_array_i[j].eq(AnySeq(dut.array_size))
            comb += dut.data_i[j].eq(AnySeq(16+128))

AnySeq is for synchronous data where the value changes on every clock.
use AnyConst instead which will not change.


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