From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Paul Mackerras <paulus@ozlabs.org>
Cc: "openpower-hdl-cores@mailinglist.openpowerfoundation.org"
<openpower-hdl-cores@mailinglist.openpowerfoundation.org>,
Libre-RISCV General Development
<libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] microwatt tlb
Date: Mon, 30 Mar 2020 09:35:19 +0000
Message-ID: <CAPweEDyFczA+w91eehZvRu+E0UsoaO2N4xN98KOQ4dkAaeagAQ@mail.gmail.com> (raw)
In-Reply-To: <20200330033002.GB15134@blackberry>
On Monday, March 30, 2020, Paul Mackerras <paulus@ozlabs.org> wrote:
>
> Thanks for the comments and the pointers. We do already have stall
> signals in microwatt, but the way it works is pretty simple so far.
*great* :)
> The pipelined, in-order execution structure basically comes from
> Anton's initial work, so I don't think we'll be throwing that out.
> We will continue to make readability and understandability a focus,
> and I for one will try to add more code comments as I work on it to
> make it easier to follow.
it's pretty damn good already, paul. one suggestion, put spec version book
section and pagenum into the comments?
btw the parsing of 3.0B PDF integer, LDST and Logical ops went "ok",
codegenerator first syntax recognising simple lines (RT) <- X[56]*4
we will need at least 3 generators (64 bit c code for pearpc, python
simulator, and nmigen) so will make it modular, therefore creating VHDL and
Chisel generators that autocreate code fragments should be a two day job
each and would result in autogenerated HDL for 80% of the 3.0B spec (!)
l.
--
---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
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Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-27 2:15 Luke Kenneth Casson Leighton
2020-03-30 3:30 ` [libre-riscv-dev] [OpenPOWER-HDL-Cores] " Paul Mackerras
2020-03-30 9:35 ` Luke Kenneth Casson Leighton [this message]
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