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From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: [libre-riscv-dev] parser precedence, code review / checking needed
Date: Fri, 3 Apr 2020 16:19:36 +0100
Message-ID: <CAPweEDygK1iT_u0Y9zVGNNX91Ndyd7FQM9hm+Yr3_KJnWuL+ig@mail.gmail.com> (raw)

if anyone knows how to resolve operator precedence, my logic-dyslexia
is kicking in and i am having difficulty working out which operators
are supposed to be in which order, for bit-wise AND, OR, and
PLUS/MINUS, MUL/DIV.  someone else did the PLUS/MINUS MUL/DIV, i'm
attempting to add AND and OR and am getting it wrong

here's how python-ply is supposed to work:
http://www.dabeaz.com/ply/ply.html#ply_nn27

here's a patch showing the relevant files involved:
https://git.libre-riscv.org/?p=soc.git;a=commitdiff;h=39c8314f9a14fb5351a9dcbc8bd37753bdcd0fee

executing "python3 soc/decoder/power_pseudo.py" is a good test, with
this being good example code:
+cmpi = """
+in_range <-  (x | y) & (a | b)
+in_range <-  (x + y) - (a + b)
+"""

help appreciated.

l.

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Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-04-03 15:19 Luke Kenneth Casson Leighton [this message]
2020-04-03 18:22 ` Jacob Lifshay
2020-04-03 18:49   ` Luke Kenneth Casson Leighton
2020-04-03 20:08     ` Jacob Lifshay
2020-04-03 21:44       ` Luke Kenneth Casson Leighton
2020-04-03 20:41   ` Hendrik Boom

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