[libre-riscv-dev] Function Units "patch-up" linking to Comp Unit code

From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: [libre-riscv-dev] Function Units "patch-up" linking to Comp Unit code
Date: Sat, 23 May 2020 19:23:05 +0100
Message-ID: <CAPweEDyo_FNgRXAEt2x0ZY0aaCbH9ukVKh_PEsLkPhTfGtbYMQ@mail.gmail.com> (raw)

right.  finally.  with regspecs in place, and the pipelines in place,
*finally* we can link them up together:
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/compunits.py;hb=HEAD

MultiCompUnit has been "morphed" to be completely FSM / Pipeline
agnostic.  it knows *nothing* about the data it's dealing with: names
or quantity of input signals, names or quantity of output signals,
absolutely nothing.  (oh, Cesar, Michael: except for the fact that RA
can be zero, and RB can be an immediate).

the *only* way to tell MultiCompUnit the information about the ALU
it's been asked to look after: regspecs.  i've documented the format,
here:
https://libre-soc.org/3d_gpu/architecture/regfile/

any questions please ask.

l.

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