From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: [libre-riscv-dev] daily kan-ban update 03aug2020
Date: Mon, 3 Aug 2020 18:46:46 +0100
Message-ID: <CAPweEDyzGpVwcHbmnpBLZOZ0=FY3SEA-sVMmmwJ1hhprAkoiig@mail.gmail.com> (raw)
tasks:
*
https://bugs.libre-soc.org/showdependencytree.cgi?id=383&maxdepth=1&hide_resolved=1
today:
* nmigen IRC meeting (in 15 mins)
* linked DMI interface to core and got reset, start and stop working.
i need to test single-step as well as add regfile reading and being able to
get MSR and the PC.
at that point i can modify the litex sim.py to put either core in
singlestep mode and dump out registers and the PC, sequentially.
l.
--
---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
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Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-03 17:46 Luke Kenneth Casson Leighton [this message]
2020-08-03 18:23 ` Tobias Platen
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