From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] more compatible alternative to BE instructions on LE processor
Date: Wed, 13 May 2020 09:09:08 +0100
Message-ID: <CAPweEDzCDDW20qLwiTtRCCUcBoOSuojcdQ8AJaiy5t1j=fP=4w@mail.gmail.com> (raw)
In-Reply-To: <20200513092953.f9475239874f2b1ff1f29fd3@gmx.com>
On Wed, May 13, 2020 at 7:29 AM Lauri Kasanen <cand@gmx.com> wrote:
> The PowerISA 3.1 doc adds a 32-bit prefix (page 46 of the pdf (reader),
> page 22 of the official naming). I didn't go into details, but for such
> plans it'd be good to take into account.
ok that entire section covers a new (extended, 64-bit) instruction
format, including new extended immediates, vector-masks and so on.
it uses major opcode 0b0000001 to do so.
however unlike what we propose (and, crucially, propose to put behind
a mode-switch bit):
* the scheme critically depends on the instructions being chunked into
32-bit sections
* 48-bit and 16-bit instruction encodings are impossible
* we need far more bits (11 bits for C, 11 bits for SVP P48 and 27
bits for SVP P64) than can fit after *one* major opcode.
16 (prefix) minus 6 (major opcode) is 10. that is not enough to fit
11 bits of SVP P48.
l.
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Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-13 2:56 Jacob Lifshay
2020-05-13 6:29 ` Lauri Kasanen
2020-05-13 8:09 ` Luke Kenneth Casson Leighton [this message]
2020-05-13 8:17 ` Luke Kenneth Casson Leighton
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