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From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: [libre-riscv-dev] wishbone does not have byte-enable (but it does have user-tags)
Date: Tue, 9 Jun 2020 18:10:30 +0100
Message-ID: <CAPweEDzJk8kSdabL3P9VCaE-UyusYtTpBC6kH6LovoucjxJNTQ@mail.gmail.com> (raw)

http://cdn.opencores.org/downloads/wbspec_b4.pdf

one of the things that i have assumed is possible to do in wishbone is
to have a bank of byte-enable lines for the memory read/write
requests.  am i correct in thinking that this is what "sel" (as an
array) is for?

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/minerva/wishbone.py;hb=HEAD#l16

also i've noticed that there is the concept of user and cycle "tags"
which can be optionally added.  this would give us a way to do
cache-line tagging and many other things.

l.

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Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-09 17:10 Luke Kenneth Casson Leighton [this message]
2020-06-09 19:18 ` Cole Poirier
2020-06-09 20:17   ` Luke Kenneth Casson Leighton
2020-06-10 21:33     ` Cole Poirier
2020-06-10 21:50       ` Luke Kenneth Casson Leighton

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