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From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: openpower-hdl-cores@mailinglist.openpowerfoundation.org
Cc: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: [libre-riscv-dev] system call (sc) LEV "reserved field"
Date: Wed, 22 Jul 2020 15:22:43 +0100
Message-ID: <CAPweEDzJpX8mDE1QJO6=rPEQfz0jCt+Yi9sS48cE4bXcu8AwcQ@mail.gmail.com> (raw)

hi, we're just reviewing the behaviour needed when LEV != 0, and are
following what microwatt does (which does not have hypervisor support
yet)

https://bugs.libre-soc.org/show_bug.cgi?id=325#c106

so the trail - i am so glad that the PDF has cross-reference linking -
jumps from one section to another and after jumping 5 times we
eventually ascertain the hypothesis that reserved fields, if set,
should raise an "illegal instruction".

however this is so unclear (because of the referral from one section
to another) that i am seeking confirmation.  should we raise an
"illegal instruction" when "LEV > 1" on sc?

secondly, we note that "LEV=1" is for invocation of the hypervisor.
what's not clear to us is - given that we are not implementing
hypervisor - should this be *also* treated as an illegal instruction?
or, should we just leave it to fall through to trap @ addr 0x0c00, and
expect the trap *there* to notice and deal with the situation?

also: if we set the HV bit in MSR (when LEV=1) section 6.5.14 p1077
which refers us back to figure 65 on p1064, will this "break" things?

also: in microwatt, i'm not seeing the remaining bits which appear [to
need to] be set.

https://github.com/antonblanchard/microwatt/blob/master/execute1.vhdl#L479
            ctrl_tmp.msr(MSR_SF) <= '1';
            ctrl_tmp.msr(MSR_EE) <= '0';
            ctrl_tmp.msr(MSR_PR) <= '0';
            ctrl_tmp.msr(MSR_IR) <= '0';
            ctrl_tmp.msr(MSR_DR) <= '0';
            ctrl_tmp.msr(MSR_RI) <= '0';
            ctrl_tmp.msr(MSR_LE) <= '1';

these appear to be correct as defined according to figure 65 (p1063)

however the remaining actions do not seem to be implemented (p1064):

     Bits bit 5, TM, VEC, VSX, PR, FP, and PMM are set to 0.
     The TE field is set to 0b00.
     TM, FP, VEC, VSX, and bit 5 are set to 0.

question: what effect would it have - bear in mind that we are
following microwatt - if we implemented these changes to MSR?  bear in
mind that we ignore most of them at the moment (MSR.LE being one
notable exception), so the question is, in effect: does the Linux
kernel *also* ignore them?

tia,

l.

---
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Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-22 14:22 Luke Kenneth Casson Leighton [this message]
2020-07-22 22:47 ` [libre-riscv-dev] [OpenPOWER-HDL-Cores] " Paul Mackerras
2020-07-22 23:41   ` [libre-riscv-dev] " Luke Kenneth Casson Leighton
2020-07-23  0:52     ` [libre-riscv-dev] [OpenPOWER-HDL-Cores] " Benjamin Herrenschmidt
2020-07-23  4:16       ` [libre-riscv-dev] " Luke Kenneth Casson Leighton
2020-07-23 22:25         ` Benjamin Herrenschmidt
2020-07-24 16:53           ` Luke Kenneth Casson Leighton
2020-07-27  4:29             ` Benjamin Herrenschmidt
2020-07-27  8:00               ` Luke Kenneth Casson Leighton
2020-07-27  9:07                 ` [libre-riscv-dev] [OpenPOWER-HDL-Cores] " Hugh Blemings
2020-07-27  9:43                   ` Luke Kenneth Casson Leighton
2020-07-23  3:14     ` Paul Mackerras
2020-07-23  4:20       ` [libre-riscv-dev] " Luke Kenneth Casson Leighton

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