From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] daily kan-ban update 25may2020
Date: Mon, 25 May 2020 23:45:39 +0100
Message-ID: <CAPweEDzN43JyCZRuK20tqQtr2RRRJRQFdLRLPE6eb_-7ScB4JQ@mail.gmail.com> (raw)
In-Reply-To: <EF27EE71-46C9-426B-93EC-A7DDC61E804E@getmailspring.com>
On Monday, May 25, 2020, Cole Poirier <colepoirier@gmail.com> wrote:
> On May 25 2020, at 2:35 pm, Luke Kenneth Casson Leighton <lkcl@lkcl.net>
> wrote:
> > in your wiki home page you will find a link to bugs assigned to you. the
> > default action is basically "monitor and do that list".
>
> Thanks that makes it easy. I saw you assigned me 'Bug 337 - Convention
> for register outputs in *OutputData structures is to use "Data"', and
> looked at your comment. Is this simply reorg or is there something
> additional I should be aware of?
ah i think i kinda did that one yesterday.
>
> > one to add:
> >
> > if you can also find the "interfaces" issue, and assign it to
> > yourself, you
> > will see a list of interfaces in the last comment, including "serialized
> > irq" which you shouls find somewhere from raptor engineering.
> >
> > can you track the source code down, add them to the wiki under the right
> > subdurectory (shakti mclass) and also crossreference them in the
> bugtracker?
>
>
> Are you referring to "Bug 304 - Define minimum viable interface set for
> 180nm ASIC", comment #6?
yes.
> ```
> Luke Kenneth Casson Leighton 2020-05-20 23:14:26 BST
>
> conversation notes from Tim (Raptor Engineering)
>
> priority:
>
> * 2x SPI master
> * 4x I2C master
> * 2x UART
> * 4x LPC master
> * EINT* Serialsed IRQ (LPC, from PCIe) - 15 or so IRQs, these are
> PC>PCIe>OpenPower mappings
>
> Quad SPI raptorengineering
> LPC bridge github raptorengineering
> ```
>
> I searched for "raptor serialized irq, and only found references to
> raptors lpc-spi-bridge-fpga gitlab repo. Is this what we need
> https://gitlab.raptorengineering.com/raptor-engineering-public/lpc-spi-
> bridge-fpga?
that sort of thing.
we need to find the full implementation, an actual serialized-irq master
> An in terms of adding the source code to the wiki,
> do you want me to
> just copy and paste the 1000+ line verilog file or files to the
> soc/libreriscv/shakti/m_class directory?
no! a wiki is not a source code repository, it is for documentation
> Or do you want me to do
> something similar to what you did for sdram.mdwn in the same directory?
yes.
>
> ```
> # SDRAM
>
> * <https://bitbucket.org/casl/c-class/src/3fba75dfbd0c64815eb8ec6dc96566
> 6812c44bae/src/peripherals/sdram/?at=master>
> * <https://opencores.org/projects/sdr_ctrl>
> ```
>
> Cole
>
> _______________________________________________
> libre-riscv-dev mailing list
> libre-riscv-dev@lists.libre-riscv.org
> http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev
>
--
---
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Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-25 12:30 Luke Kenneth Casson Leighton
2020-05-25 14:20 ` Tobias Platen
2020-05-25 14:27 ` Luke Kenneth Casson Leighton
2020-05-25 16:39 ` Michael Nolan
2020-05-25 18:29 ` Luke Kenneth Casson Leighton
2020-05-25 17:41 ` Cesar Strauss
2020-05-25 18:47 ` Luke Kenneth Casson Leighton
2020-05-25 19:30 ` Jacob Lifshay
2020-05-25 19:40 ` Luke Kenneth Casson Leighton
2020-05-25 21:06 ` Cole Poirier
2020-05-25 21:35 ` Luke Kenneth Casson Leighton
2020-05-25 22:11 ` Cole Poirier
2020-05-25 22:45 ` Luke Kenneth Casson Leighton [this message]
2020-05-25 23:22 ` Cole Poirier
2020-05-25 23:40 ` Luke Kenneth Casson Leighton
2020-05-26 0:11 ` Cole Poirier
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