From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: [libre-riscv-dev] daily kan-ban update 12jul2020
Date: Sun, 12 Jul 2020 13:43:59 +0100
Message-ID: <CAPweEDzUMD5Ykn4=td7oi2xxZBsdKr5SF0k=crGGXwCi6Ra+_A@mail.gmail.com> (raw)
tasks:
https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1
yesterday:
* big addition of bigendian flag throughout code (qemu, ISACaller, tests)
* started running helloworld.bin again
today:
* fixed simple bug in PowerDecoder2, OP_B was not setting LR register write
* added LD/ST cacheing-inhibit instructions
so that's enough to get helloworld "operational" as far as running
without a UART peripheral is concerned. the next stage will be to
drop a UART peripheral (simulated or otherwise) onto the memory bus.
these are what the ld/st cache-inhibit instructions are supposed to be
used for, to access the peripheral at address 0xc0000000.
l.
---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
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Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-12 12:43 Luke Kenneth Casson Leighton [this message]
2020-07-13 1:48 ` Jacob Lifshay
2020-07-13 3:49 ` Jacob Lifshay
2020-07-13 9:42 ` Luke Kenneth Casson Leighton
2020-07-13 9:51 ` Jacob Lifshay
2020-07-13 9:58 ` Luke Kenneth Casson Leighton
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