[libre-riscv-dev] first version of test issuer is functional

From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: [libre-riscv-dev] first version of test issuer is functional
Date: Wed, 17 Jun 2020 12:30:44 +0100
Message-ID: <CAPweEDzYoEkX8PSh+7gkU4qF5-b9afgrjHS1onsxg+iJV4qnVw@mail.gmail.com> (raw)

i got these working, overnight:

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/simple/test/test_issuer.py;hb=HEAD
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/simple/issuer.py;hb=HEAD

this is a module and associated unit test that are specifically
designed to be as simple and as absolutely clear as possible, and are
specifically intended to test the combined Function Units yet at the
same time actually allow "arbitrary code execution" including loops.

at present the instructions are pushed into a TestMemory (16 words),
and read out sequentially, disregarding changes made by the Branch
Unit.  this because that is what the Simulator currently does, and so
consequently all the Function Unit tests are *also* designed to
*produce* changes to the PC, but not to actually listen to them.

to be able to run programs in a loop (and have them verified) it is
necessary to first to go back to the qemu-simulator comparator
(test_sim.py), add the capability to the *Simulator* (ISACaller) to be
able to read instructions from a memory area, and then finally come
back to the hardware and do the same thing.

given that we need to be able to run the original unit tests as well
(the ones that just receive a list of instructions), this "listening
to PC" will have to be done as a mode, both by the simulator and by
the hardware.

l.

---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

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