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From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] spr formal proof, NLNet RFPs
Date: Fri, 17 Jul 2020 21:40:08 +0100
Message-ID: <CAPweEDzZmj1akARPjgV7Z_VDi+AKm+P48cC8pZeU68i-D6mDUg@mail.gmail.com> (raw)
In-Reply-To: <CAEz=sokKL4aCbLYj7R4=_sedycOZvrcN0jHZUr9zH6EkUR2OBQ@mail.gmail.com>

On Friday, July 17, 2020, Samuel Falvo II <sam.falvo@gmail.com> wrote:

> Registered as a personal account for the time being.
>
> I think, in the interests of just practicing on the code-base, I'll
> stick with the ALU FV requirements for the time being.  I'm just
> becoming comfortable with spelunking that code.  I'd like to feel
> useful for a while before I start another task.  :)


:)

well, the ALU pipeline correctness proof is done already, and the Logical
one.

Trap is like the "next least complicated" one, pretty much along the same
lines as SPR.

https://bugs.libre-soc.org/show_bug.cgi?id=421

MUL is more challenging (more involved) as there are sign-swapping, 32 bit,
64 bit, etc involved.

DIV *might* actually be straightforward to do hum except as a FSM it'll
need some timing logic.

l.



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Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-17 18:51 Luke Kenneth Casson Leighton
2020-07-17 20:15 ` Samuel Falvo II
2020-07-17 20:40   ` Luke Kenneth Casson Leighton [this message]

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