[libre-riscv-dev] 3.0B PDF spec parser and first auto-generator working well

From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: openpower-hdl-cores@mailinglist.openpowerfoundation.org,
	 Libre-RISCV General Development
	<libre-riscv-dev@lists.libre-riscv.org>
Subject: [libre-riscv-dev] 3.0B PDF spec parser and first auto-generator working well
Date: Sat, 4 Apr 2020 14:33:58 +0100
Message-ID: <CAPweEDzbq3xJRu0MoV1L3YVjcsXpdCqwSWEjZ1okD3qdCcpNcg@mail.gmail.com> (raw)

making good progress.  this (which can be seen here
https://libre-riscv.org/openpower/isa/fixedarith/)

vvvvvv
# Add Immediate Shifted

D-Form

* addis RT,RA,SI

    if RA = 0 then RT <- EXTS(SI || [0]*16)
    else           RT <- (RA) + EXTS(SI || [0]*16)

Special Registers Altered:

    None
^^^^^

gets turned into this:

vvvv
# auto-generated, do not edit
from soc.decoder.helpers import (EXTS,)
class fixedarith(ISACaller):
    def op_addis(self, RA):
        if RA == 0:
            RT = EXTS(concat(SI, concat(0, repeat=16)))
        else:
            RT = RA + EXTS(concat(SI, concat(0, repeat=16)))
        return (RT,)
    instrs = {}
    instrs['addis'] = (op_addis, ['RA'], [], ['RT']) # records input
and output regs
^^^^

no "laborious manually-written simulator code" was written.  the next
phase is, obviously, to try actually executing these code-fragments.
that's what the base-class "ISACaller" is for.

l.

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