[libre-riscv-dev] priority picker

From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: [libre-riscv-dev] priority picker
Date: Tue, 17 Mar 2020 21:51:57 +0000
Message-ID: <CAPweEDzz2P0Z+JAqPkoV=QVo-EaRayHkPTKhzpLaKpc_ShyZJA@mail.gmail.com> (raw)

https://git.libre-riscv.org/?p=nmutil.git;a=blob;f=src/nmutil/picker.py;h=0e50fd24f1131cb40ff306030f0dcfb107d0c22e;hb=a6130a92485d572182ab80a2da279997388ef52e#l64

i just created something called "MultiPriorityPicker" which is quite cute.
PriorityPicker is an important "selector" of which (unary-encoded).  This is
used to select which Function Unit's output will get access to a given register
file port, for example.

Except... what happens if we have multiple register file ports? (which we do)
Err... who gets access to which port?

that's what the MultiPriorityPicker is for.  basically it is an array
of PriorityPickers (see
https://libre-riscv.org/3d_gpu/architecture/6600scoreboard/)

the PriorityPickers are connected in a cascade, where the output of
each *accumulates* a mask that *prevents* downstream PriorityPickers
from picking already-picked outputs.

in addition, in order to help select a particular "port", an index
(currently in binary, i may change that to unary later) is set - again
in an incrementing cascade - such that whichever Picker's output has a
"1" set it is *guaranteed* to also be allocated a unique "index" as
well.

this "index" can be used to say which "port" on the register file, for
example, that the "Picker" is permitted to write (or read) from.

it also has uses for the LOAD/STORE buffer: namely the
Load/Store-FunctionUnit's have to know which "port" to write into the
(multi-input) LD/ST Buffer (aka cache).

all good fun.

l.

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