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From: Staf Verhaegen <staf@fibraservi.eu>
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Date: Thu, 26 Mar 2020 21:18:34 +0100
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Luke Kenneth Casson Leighton schreef op do 26-03-2020 om 13:05 [+0000]:
> On Thursday, March 26, 2020, Staf Verhaegen <staf@fibraservi.eu> wrote:
> > Would like to make separate side remark here. In ASICs MUXes are relati=
veexpensive gates with respect to delay and power. So if this principle isg=
enerally applied over the whole design it will make it difficult to make ac=
hip that is competitive in power/performance compared to ARM/x86 CPUs.
>=20
>=20
> just the ALU pipeline registers.  we felt that the advantage of being abl=
eto drop to say 500mhz and halve the number of pipeline stages to say 5, an=
dalso be able to ramp up to 1.6ghz and double bavk up to 10 stages, waswort=
h considering.

What would be the advantage over running at 800Mhz with 5 pipeline stages ?

greets,
Staf.


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