[libre-riscv-dev] Rough timing estimate in yosys

[Michael Nolan <mtnolan2640@gmail.com>]

With all the work going on designing functional units, I was wondering 
if there was a way to get a rough estimate of the maximum frequency a 
module can run at. I can get the longest path from running yosys -p 
"read_ilang module.il; synth; ltp", but that just prints out the cells 
between register A and register B. I realize that the actual timing is 
going to depend on layout, but is there a way to get a rough estimate, 
say by passing in a cell library or just a rule of thumb of ~500ps per cell?


On a semi-related note, running ltp on a pipeline shows that there's a 
bunch of loops.

 From running synth and ltp on the logical pipeline:

Warning: Detected loop at \stage_o$next [63] in pipe
Warning: Detected loop at \stage_o$next [62] in pipe
Warning: Detected loop at \stage_o$next [61] in pipe
Warning: Detected loop at \stage_o$next [60] in pipe
Warning: Detected loop at \stage_o$next [59] in pipe
Warning: Detected loop at \stage_o$next [58] in pipe
Warning: Detected loop at \stage_o$next [57] in pipe
Warning: Detected loop at \stage_o$next [56] in pipe
Warning: Detected loop at \stage_o$next [55] in pipe
Warning: Detected loop at \stage_o$next [54] in pipe
Warning: Detected loop at \stage_o$next [53] in pipe
Warning: Detected loop at \stage_o$next [52] in pipe
Warning: Detected loop at \stage_o$next [51] in pipe
Warning: Detected loop at \stage_o$next [50] in pipe
Warning: Detected loop at \stage_o$next [49] in pipe
Warning: Detected loop at \stage_o$next [48] in pipe
Warning: Detected loop at \stage_o$next [47] in pipe
Warning: Detected loop at \stage_o$next [46] in pipe

Is this supposed to happen?

--Michael


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