From: bugzilla-daemon@libre-riscv.org
To: libre-riscv-dev@lists.libre-riscv.org
Subject: [libre-riscv-dev] [Bug 256] New: Enhancements to an OpenPOWER ISA-level Simulator are needed
Date: Fri, 13 Mar 2020 18:26:47 +0000
Message-ID: <bug-256-13@http.bugs.libre-riscv.org/> (raw)
http://bugs.libre-riscv.org/show_bug.cgi?id=256
Bug ID: 256
Summary: Enhancements to an OpenPOWER ISA-level Simulator are
needed
Product: Libre Shakti M-Class
Version: unspecified
Hardware: PC
OS: Linux
Status: CONFIRMED
Severity: enhancement
Priority: ---
Component: Source Code
Assignee: lkcl@lkcl.net
Reporter: lkcl@lkcl.net
CC: libre-riscv-dev@lists.libre-riscv.org
NLnet milestone: ---
The vectorisation and other improvements needed for the LibreSOC need a
simulator in order to test out applications at the assembly-code / binary
level, prior to implementation in hardware. An instruction-compatible
simulator will be able to execute programs at reasonable speed whereas the
hardware-level simulator will be hundreds of thousands of times slower. gem5
is a suitable starting point, and the modifications to spike (RV simulator)
need to be ported to it:
https://git.libre-riscv.org/?p=riscv-isa-sim.git;a=tree;h=refs/heads/sv;hb=refs/heads/sv
see this:
https://www.gem5.org/documentation/general_docs/architecture_support/
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Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-13 18:26 bugzilla-daemon [this message]
2020-03-13 18:29 ` [libre-riscv-dev] [Bug 256] " bugzilla-daemon
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