[libre-riscv-dev] [Bug 267] The efficiency of adder/subtractor

[bugzilla-daemon@libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=267

--- Comment #4 from Jock Tanner <tanner.of.kha@gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #3)
> if you can put some links here as to what you're comparing (descriptions,
> tutorials, gate-level diagrams) i can get up to speed and follow the
> conversation.

I mostly rely on a college textbook by David & Sarah Harris, named “Digital
Design and Computer Architecture”. I read it only in Russian though. The book
has a very detailed explanation of carry-lookahead adder, with truth tables and
schematics.

Some knowledge can even be found in Wiki [1].

Very roughly speaking, N-bit ripple-carry adder takes a*N transistors and b*N
time for calculation, while straight-out carry-lookahead adder takes a^N
transistors and b time. AFAIK in practical ALU design they always make a
compromise between the two. And I just wonder what kind of compromise could be
suitable for *reconfigurable*, high-speed ALU.

I imagine something cascadable, like 74181 bit-slice ALUs + 74182 carry
generators [2], but with 'plexors in between. But the speed of such a design
may be questionable.

[1] https://en.wikipedia.org/wiki/Adder_(electronics)
[2] https://en.wikipedia.org/wiki/74181

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