[libre-riscv-dev] [Bug 289] New: LD/ST Function Unit address match "vector" optimisation

[bugzilla-daemon@libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=289

            Bug ID: 289
           Summary: LD/ST Function Unit address match "vector"
                    optimisation
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: lkcl@lkcl.net
          Reporter: lkcl@lkcl.net
                CC: libre-riscv-dev@lists.libre-riscv.org
   NLnet milestone: ---

at the L0 Cache/Buffer level, and in the address-match matrix, a massive
array of XOR gates (comparators) is needed.  this is a huge power drain.

however back at the vector-issue phase, information is known between
multiple units: there is a very high probability that related element
addresses will not have changed (especially on element-strided
LD/STs) and, furthermore, it is very easy to detect.

https://groups.google.com/d/msg/comp.arch/cbGAlcCjiZE/IDhmQPS6AAAJ

therefore as an enhancement, when Vector LD/STs are involved, provide
additional information down to the address-match and L0 cache/buffer
that saves huge amounts of power.

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