From: bugzilla-daemon@libre-soc.org
To: libre-riscv-dev@lists.libre-riscv.org
Subject: [libre-riscv-dev] [Bug 318] fix LDSTCompUnit
Date: Mon, 18 May 2020 16:56:22 +0000
Message-ID: <bug-318-13-A2G1v56yet@https.bugs.libre-soc.org/> (raw)
In-Reply-To: <bug-318-13@https.bugs.libre-soc.org/>
https://bugs.libre-soc.org/show_bug.cgi?id=318
--- Comment #14 from Cesar Strauss <cestrauss@gmail.com> ---
Dear Luke,
I see uses of "latchregister" and "SRLatch" in code. In the nMigen library,
they are internally implemented with synchronous logic, although partly
resembling the function of their asynchronous equivalents.
Do you, by any chance, intend to replace them, in the ASIC, with real
asynchronous latches? As depicted in several diagrams at
https://libre-soc.org/3d_gpu/architecture/6600scoreboard/ ?
Regards,
Cesar
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Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-17 10:08 [libre-riscv-dev] [Bug 318] New: " bugzilla-daemon
2020-05-17 10:09 ` [libre-riscv-dev] [Bug 318] " bugzilla-daemon
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