[libre-riscv-dev] [Bug 329] coriolis2 experiment layout for Dependency Matrices

[bugzilla-daemon@libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=329

Jean-Paul.Chaput@lip6.fr changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |Jean-Paul.Chaput@lip6.fr

--- Comment #6 from Jean-Paul.Chaput@lip6.fr ---
(In reply to Luke Kenneth Casson Leighton from comment #5)
> i just also added a second one to experiment8 as an illustration, it is an
> FU-Regs Matrix with the following parameters:
> 
> * Number of Regs:                          4 (to keep it small as a demo)
> * Number of Function Units:                3 (likewise)
> * Number of Regfile Read ports protected:  2
> * Number of Regfile Write ports protected: 2
> 
> these numbers can and will vary.  we have *four* Register Files to
> protect with these Matrices.  five when we have FP support.

Hello Luke,

I'm looking closely to the examples but I still have problem understanding the
matrix
nature of the design. As a first I would like to concentrate on the FU-FU
matrix, which,
if I understand well, manage the read/write dependencies between FUs and
generate the
Go_Read & Go_Write signals towards the CU (and some other signals).

There is two "level" of matrixes:

1. The architectural level (that is close to what you do) and the one I cannot
clearly
   guess. With 3 FU, is there a 3x3 matrix or 3 FU blocks only, and in the
later case,
   it may not be a matrix but just a row or a column.
     But maybe I make confusion between FU and the dependency matrix of the
FUs.

2. The layout (cell level) into which the cells of *one* FU (or whatever
sub-block)
   are also arrayed in a matrix. As we may not put all the cells of a block in
just
   one row.

So would it be possible to send examples where one block of the matrix (in the
sense of 1.) is clearly identified (best would be that it is put in a
sub-block) ?

Or, if it is really inconvenient due to the way the design is described at
nMigne level,
list me what I/O signals (which bit of vectors) are specific to one element of
the
matrix ?

A slow learner.

PS: I still not completely understand the color coding of the scoreboard
schematic.
    Is the size and position of the little blue/yellow/green squares inside the
red one
    significant?

-- 
You are receiving this mail because:
You are on the CC list for the bug.
_______________________________________________
libre-riscv-dev mailing list
libre-riscv-dev@lists.libre-riscv.org
http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev