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Date: Sun, 24 May 2020 15:07:49 +0000
X-Bugzilla-Reason: CC
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X-Bugzilla-Product: Libre-SOC's first SoC
X-Bugzilla-Component: Source Code
X-Bugzilla-Version: unspecified
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X-Bugzilla-Severity: enhancement
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Message-ID: <bug-336-13-tDdjJZEiyz@https.bugs.libre-soc.org/>
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Subject: [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA
 (src1) can be zero
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