From: bugzilla-daemon@libre-soc.org
To: libre-riscv-dev@lists.libre-riscv.org
Subject: [libre-riscv-dev] [Bug 341] New: unit tests needed for soc.fu.compunits (shared with soc.fu.*/test_pipe_caller.py)
Date: Sat, 23 May 2020 22:50:53 +0000
Message-ID: <bug-341-13@https.bugs.libre-soc.org/> (raw)
https://bugs.libre-soc.org/show_bug.cgi?id=341
Bug ID: 341
Summary: unit tests needed for soc.fu.compunits (shared with
soc.fu.*/test_pipe_caller.py)
Product: Libre-SOC's first SoC
Version: unspecified
Hardware: PC
OS: Linux
Status: CONFIRMED
Severity: enhancement
Priority: ---
Component: Source Code
Assignee: lkcl@lkcl.net
Reporter: lkcl@lkcl.net
CC: libre-riscv-dev@lists.libre-riscv.org
NLnet milestone: ---
we need some test infrastructure that does exactly the same as
every single one of the test_pipe_caller.py unit tests, except
using ALUFunctionUnit, CRFunctionUnit etc. instead of
ALUBasePipe+ALUPipeSpec, CRBasePipe+CRPipeSpec etc.
the only pieces of code that need to change to achieve this is
how the inputs are set up, and the outputs obtained.
this basically means generalising each test_pipe_caller.py
TestRunner.run_all().process() function, so that instead
of explicitly targetting the alu instance:
vld = yield alu.n.valid_o
while not vld:
yield
vld = yield alu.n.valid_o
yield
alu_out = yield alu.n.data_o.o
instead it allows a parameterised selection of the MultiCompUnit API /
data-synchronisation method (see experiment/compalu_multi.py tests):
yield dut.issue_i.eq(1)
yield
yield dut.issue_i.eq(0)
yield
yield dut.rd.go.eq(0b11)
while True:
yield
rd_rel_o = yield dut.rd.rel
print ("rd_rel", rd_rel_o)
if rd_rel_o:
break
(actually, this ties in with Cesar's task, somewhat).
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Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-23 22:50 bugzilla-daemon [this message]
2020-05-23 22:52 ` [libre-riscv-dev] [Bug 341] " bugzilla-daemon
2020-05-23 22:58 ` bugzilla-daemon
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