From: bugzilla-daemon@libre-soc.org
To: libre-riscv-dev@lists.libre-riscv.org
Subject: [libre-riscv-dev] [Bug 344] New: missing mtmsr and mfsprd
Date: Sun, 24 May 2020 14:27:44 +0000
Message-ID: <bug-344-13@https.bugs.libre-soc.org/> (raw)
https://bugs.libre-soc.org/show_bug.cgi?id=344
Bug ID: 344
Summary: missing mtmsr and mfsprd
Product: Libre-SOC's first SoC
Version: unspecified
Hardware: PC
OS: Mac OS
Status: CONFIRMED
Severity: enhancement
Priority: ---
Component: Source Code
Assignee: lkcl@lkcl.net
Reporter: lkcl@lkcl.net
CC: libre-riscv-dev@lists.libre-riscv.org
NLnet milestone: ---
missing two operations from sprset.mdwn and also minor_op31.csv
Move To Machine State Register
X-form
mtmsr RS,L
if L = 0 then
MSR48 ← (RS)48 | (RS)49
MSR58 <- ((RS)58 | (RS)49)& ¬(MSR41 & MSR3 & (¬(RS)49))
MSR59 <- ((RS)59 | (RS)49)& ¬(MSR41 & MSR3 & (¬(RS)49))
MSR32:40 42:47 49:50 52:57 60:62 <- (RS)32:40 42:47 49:50 52:57 60:62
else
MSR48 62 ← (RS)48 62
Move To Machine State Register Doubleword
X-Form
mtmsrd RS,L
if L = 0 then
MSR48 ← (RS)48 | (RS)49
MSR58 <- ((RS)58 | (RS)49)& ¬(MSR41 & MSR3 & (¬(RS)49))
MSR59 <- ((RS)59 | (RS)49) & ¬(MSR41 & MSR3 & (¬(RS)49))
MSR0:2 4:40 42:47 49:50 52:57 60:62 ← (RS)0:2 4 6:40 42:47 49:50 52:57 60:62
else
MSR48 62 ← (RS)48 62
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