From: bugzilla-daemon@libre-soc.org
To: libre-riscv-dev@lists.libre-riscv.org
Subject: [libre-riscv-dev] [Bug 358] New: new MCU-ALU test picked up RC / OE / CR handling issue
Date: Sat, 30 May 2020 19:47:48 +0000
Message-ID: <bug-358-13@https.bugs.libre-soc.org/> (raw)
https://bugs.libre-soc.org/show_bug.cgi?id=358
Bug ID: 358
Summary: new MCU-ALU test picked up RC / OE / CR handling issue
Product: Libre-SOC's first SoC
Version: unspecified
Hardware: PC
OS: Linux
Status: CONFIRMED
Severity: enhancement
Priority: ---
Component: Source Code
Assignee: lkcl@lkcl.net
Reporter: lkcl@lkcl.net
CC: libre-riscv-dev@lists.libre-riscv.org
NLnet milestone: ---
yippee! a new unit test (test_alu_compunit.py) just picked up that
we are using rc from Decode2ExecuteType in the wrong way. as RC and
OE are both of type "Data", the test needs to be on "rc_ok" enabled.
i think.
the symptoms: test_alu_compunit.py fails because CR0 is not being
outputted on OP_CMP. as in: cr0.ok is not being set.
it's not being set because in CommonOutputStage:
comb += self.o.cr0.data.eq(cr0)
comb += self.o.cr0.ok.eq(op.rc.rc & op.rc.rc_ok) # CR0 to be set
op.rc.rc & op.rc.rc_ok is *zero*, and yet the test in test_output_caller.py
(and test_alu_compunit.py) is this:
def check_extra_alu_outputs(self, alu, dec2, sim, code):
rc = yield dec2.e.rc.data
if rc:
....
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Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-30 19:47 bugzilla-daemon [this message]
2020-05-30 19:48 ` [libre-riscv-dev] [Bug 358] " bugzilla-daemon
2020-05-30 20:39 ` bugzilla-daemon
2020-05-30 21:22 ` bugzilla-daemon
2020-06-01 23:24 ` bugzilla-daemon
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