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From: bugzilla-daemon@libre-soc.org
To: libre-riscv-dev@lists.libre-riscv.org
Subject: [libre-riscv-dev] [Bug 362] New: improvements to nmigen and yosys
Date: Thu, 04 Jun 2020 13:40:01 +0000
Message-ID: <bug-362-13@https.bugs.libre-soc.org/> (raw)

https://bugs.libre-soc.org/show_bug.cgi?id=362

            Bug ID: 362
           Summary: improvements to nmigen and yosys
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: lkcl@lkcl.net
          Reporter: lkcl@lkcl.net
                CC: libre-riscv-dev@lists.libre-riscv.org
   NLnet milestone: ---

improvements to nmigen and yosys are needed, including CXXSim, a
new backend for yosys that allows a 20 to 100x performance increase
in simulation speed.

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Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-04 13:40 bugzilla-daemon [this message]
2020-06-04 13:42 ` [libre-riscv-dev] [Bug 362] " bugzilla-daemon
2020-06-06 23:55 ` bugzilla-daemon

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