From: bugzilla-daemon@libre-soc.org
To: libre-riscv-dev@lists.libre-riscv.org
Subject: [libre-riscv-dev] [Bug 363] New: inconsistency between isel and mfcr unit test on bit-ordering of CR
Date: Thu, 04 Jun 2020 19:51:11 +0000
Message-ID: <bug-363-13@https.bugs.libre-soc.org/> (raw)
https://bugs.libre-soc.org/show_bug.cgi?id=363
Bug ID: 363
Summary: inconsistency between isel and mfcr unit test on
bit-ordering of CR
Product: Libre-SOC's first SoC
Version: unspecified
Hardware: PC
OS: Mac OS
Status: CONFIRMED
Severity: enhancement
Priority: ---
Component: Source Code
Assignee: lkcl@lkcl.net
Reporter: lkcl@lkcl.net
CC: libre-riscv-dev@lists.libre-riscv.org
NLnet milestone: ---
very weird.
when storing the bits in the CR (full_cr vs individual CRs) the ordering
is wrong.
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Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-04 19:51 bugzilla-daemon [this message]
2020-06-04 19:55 ` [libre-riscv-dev] [Bug 363] " bugzilla-daemon
2020-06-04 20:52 ` [libre-riscv-dev] [Bug 363] inconsistency between isel and mfcr and crand " bugzilla-daemon
2020-06-05 3:55 ` bugzilla-daemon
2020-06-05 3:55 ` bugzilla-daemon
2020-06-05 13:39 ` bugzilla-daemon
2020-06-05 13:58 ` bugzilla-daemon
2020-06-05 19:41 ` bugzilla-daemon
2020-06-05 19:47 ` bugzilla-daemon
2020-06-07 20:19 ` bugzilla-daemon
2020-06-07 20:25 ` bugzilla-daemon
2020-06-07 20:31 ` bugzilla-daemon
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