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From: "Immanuel, Yehowshua U" <yimmanuel3@gatech.edu>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] Advanced Topics on RISCV
Date: Tue, 24 Mar 2020 12:58:29 +0000
Message-ID: <04CF3503-5B4C-4BDE-88AD-E2FB12F37665@gatech.edu> (raw)
In-Reply-To: <CAPweEDzo=6eDRU8YhBf14JwqOn=S5vijy1+3w6T8wygXoxX2hQ@mail.gmail.com>

> given that AMOs are not very common, they basically get away with this
> approach.  however for massively-parallel SMP systems (64 cores or
> greater) this approach would begin to result in significant contention
> and slow-down of certain tasks.

So how would you get around this for >64 core RISCV CPU?

Yehowshua

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Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-24 11:51 Immanuel, Yehowshua U
2020-03-24 12:06 ` Luke Kenneth Casson Leighton
2020-03-24 12:58   ` Immanuel, Yehowshua U [this message]
2020-03-24 12:23 ` Jean-Paul Chaput
2020-03-24 13:00   ` Immanuel, Yehowshua U
2020-03-24 13:08     ` Jean-Paul Chaput

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