[libre-riscv-dev] Pinout, interfaces, Rudi, and Raptor

[libre-riscv-dev] Pinout, interfaces, Rudi, and Raptor

[Yehowshua]

Hello Luke,
	So I see we have some pinout sdefine here.

https://libre-soc.org/shakti/m_class/pinouts/ <https://libre-soc.org/shakti/m_class/pinouts/>


My suggestion is to drop the pinmux for now. We should probably update that page(or create a similar page) to reflect what we’re targeting for October.

IIRC, we’re targeting QFP. I don’t see the dimensions or form factor we’re targeting listed there however. We should talk about that.

Also, talked with Tim and SDR could work for the first SBC. LiteX also supports SDR which is good for us as it doesn’t require a PHY like DDR making it simpler.

Luke, should I connect Rudi to Tim?

Yehowshua
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Re: [libre-riscv-dev] Pinout, interfaces, Rudi, and Raptor

[Luke Kenneth Casson Leighton]

On Fri, May 8, 2020 at 3:20 PM Yehowshua <yimmanuel3@gatech.edu> wrote:
>
> Hello Luke,
>         So I see we have some pinout sdefine here.
>
> https://libre-soc.org/shakti/m_class/pinouts/ <https://libre-soc.org/shakti/m_class/pinouts/>
>
>
> My suggestion is to drop the pinmux for now.

it needs writing anyway [not to use Bluespec].  that was *another*
project that took 3 months to do and we can't really use because it's
hard-coded to what the Shakti Team use in IIT Madras.  *sigh*.

> We should probably update that page(or create a similar page) to reflect what we’re targeting for October.

already done https://libre-soc.org/180nm_Oct2020/interfaces/


> IIRC, we’re targeting QFP. I don’t see the dimensions or form factor we’re targeting listed there however. We should talk about that.
>
> Also, talked with Tim and SDR could work for the first SBC.

update interfaces page https://libre-soc.org/180nm_Oct2020/interfaces/?updated

> LiteX also supports SDR which is good for us as it doesn’t require a PHY like DDR making it simpler.

yes.  and it's silicon-proven via the Shakti Team, in their first 22nm
ASIC from 2 years ago.


> Luke, should I connect Rudi to Tim?

hmmm.... in my mind, the roles do not really match up.  they do
however with one of us (by "us" i mean you :) given that i'm trying to
focus on heavily-technical development) as the intermediary

roles:

* Rudi's asked specifically for the interfaces, he'll write a spec as
a PDF and if we say "go" he'll get on with it.
* Tim's role here is as the "customer" plus he's busy.

therefore i suggest:

* *we* need to capture the requirements (of Tim) - by "we" i mean you
* go over them, discuss and approve them (whole team)
* *then* authorise Rudi to go ahead with a design document (i send the message)
* then go over that and discuss and review it (whole team)
* *then* notify Rudi "please go ahead" (i send the message)

l.

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Re: [libre-riscv-dev] Pinout, interfaces, Rudi, and Raptor

[Staf Verhaegen]

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Yehowshua schreef op vr 08-05-2020 om 10:20 [-0400]:
> Hello Luke,	So I see we have some pinout sdefine here.
> https://libre-soc.org/shakti/m_class/pinouts/ <https://libre-soc.org/shakti/m_class/pinouts/>
> 
> My suggestion is to drop the pinmux for now. We should probably update that page(or create a similar page) to reflect what we’re targeting for October.
> IIRC, we’re targeting QFP. I don’t see the dimensions or form factor we’re targeting listed there however. We should talk about that.
> Also, talked with Tim and SDR could work for the first SBC. LiteX also supports SDR which is good for us as it doesn’t require a PHY like DDR making it simpler.

You refer to a first SBC preferably low-cost. The October prototype tape-out will not be cost-effective for that. It is a multi-project wafer. You can order extra wafers but it does mean that the cost of that wafer is divided over much less devices; meaning the cost will be around $32 per chip and some of them will not be functional; in microelectrics you never have 100% yield. Also I think there is limit on only be able to get at most 1000 chips this way.

If you want lower cost per unit you need to go for a full mask with a so-called engineering lot of 12 wafers. This will have a high startup cost. A first crude estimation is between $70000 and $75000. This give a few thousand of chips; exact number depends on the size of the chip. An extra engineering lot of 12 wafers will be around $18000.
For this it means you will need to a new tape-out so you can add extra peripherals that were not on the prototype tape-out.

greets,
Staf.


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Re: [libre-riscv-dev] Pinout, interfaces, Rudi, and Raptor

[Luke Kenneth Casson Leighton]

On Sat, May 9, 2020 at 10:12 AM Staf Verhaegen <staf@fibraservi.eu> wrote:

> You refer to a first SBC preferably low-cost. The October prototype tape-out will not be cost-effective for that. It is a multi-project wafer.

i explained this to Yehowshua, however it was off-list during a very
rapid conversation with Tim from Raptor CS  - thank you for putting
this on-list.

> You can order extra wafers but it does mean that the cost of that wafer is divided over much less devices; meaning the cost will be around $32 per chip and some of them will not be functional; in microelectrics you never have 100% yield. Also I think there is limit on only be able to get at most 1000 chips this way.

(in lower geometries on MPW Programmes, 30% yield is good going).

l.

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Re: [libre-riscv-dev] Pinout, interfaces, Rudi, and Raptor

[Yehowshua]

> On May 9, 2020, at 5:12 AM, Staf Verhaegen <staf@fibraservi.eu> wrote:
> 
> The October prototype tape-out will not be cost-effective for that. It is a multi-project wafer.

Yes we know. One of our potential customers did eventually want to do a low cost SBC - so choosing cheaper peripherals is always a good way to go.

Yehowshua
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