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From: Michael Nolan <mtnolan2640@gmail.com>
To: libre-riscv-dev@lists.libre-riscv.org
Subject: Re: [libre-riscv-dev] daily kan-ban update 19may2020
Date: Tue, 19 May 2020 13:47:28 -0400
Message-ID: <1b56d581-15d1-cc09-a581-d9547564381b@gmail.com> (raw)
In-Reply-To: <CAPweEDwRS5yHWa=qnyZhCe5tux6Q=9KiXvxg5M_x21=GZ5tnaw@mail.gmail.com>

Today I was going to try and work on the trap block, but it looks like 
Luke is already working on defining the registers for it and I don't 
want to interfere.

I was able to modify caller.py to correctly generate carries, and added 
checking of the carry bit to the alu unit tests. One snarl with that 
though is I am unable to get qemu to show modifications to the carry bit 
in XER for some reason. This isn't an issue for carry (or overflow), but 
it would be good to have for the 32 bit carry and overflow. I may need 
to hold off on the 32 bit versions until I'm able to run tests on a real 
power machine.

I also looked at the differences between nmutil.clz and nmigen's 
PriorityEncoder, and summarized them in 
https://bugs.libre-soc.org/show_bug.cgi?id=326

--Michael


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  parent reply index

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-19 11:59 Luke Kenneth Casson Leighton
2020-05-19 12:36 ` Luke Kenneth Casson Leighton
2020-05-19 16:38   ` Cesar Strauss
2020-05-19 17:13 ` Jacob Lifshay
2020-05-19 17:34   ` Luke Kenneth Casson Leighton
2020-05-19 17:47 ` Michael Nolan [this message]
2020-05-19 17:56   ` Luke Kenneth Casson Leighton
2020-05-19 18:01     ` [libre-riscv-dev] priority encoder replacement Jacob Lifshay
2020-05-19 18:46       ` Luke Kenneth Casson Leighton
2020-05-19 20:17     ` [libre-riscv-dev] daily kan-ban update 19may2020 Cole Poirier
2020-05-20  6:39 ` Tobias Platen
2020-05-20 11:28   ` Luke Kenneth Casson Leighton

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