From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] daily kan-ban update 19may2020
Date: Tue, 19 May 2020 13:36:18 +0100
Message-ID: <CAPweEDy_BOjYKNiTqBhvXXTqymFyinfJyeyC80JLoQRVyZw2tw@mail.gmail.com> (raw)
In-Reply-To: <CAPweEDwRS5yHWa=qnyZhCe5tux6Q=9KiXvxg5M_x21=GZ5tnaw@mail.gmail.com>
On Tuesday, May 19, 2020, Luke Kenneth Casson Leighton <lkcl@lkcl.net>
wrote:
except, i can't complete the diagram because i am blocked waiting for Jacob
> to do the DIV and MUL pipelines, which we have found highlights clearly
> what regs are needed in ways that a cursory examination does not reveal.
>
after doing some preliminary checks we also have a block on the reg
allocation task for a TRAP pipeline.
i think what i will do is, morph CompALUUnit to use a Record.
Cesar, CompLDSTUnit also will need converting to use a Record.
this because when grouping the CompUnits together it is a lot easier to do
so using arrays of Records.
however if i do CompALU first you will get an idea of what it will look
like and so are not surprised by code changes.
i will create "dummy" variables in the classes so that it does not require
massive code changes.
l.
--
---
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Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-19 11:59 Luke Kenneth Casson Leighton
2020-05-19 12:36 ` Luke Kenneth Casson Leighton [this message]
2020-05-19 16:38 ` Cesar Strauss
2020-05-19 17:13 ` Jacob Lifshay
2020-05-19 17:34 ` Luke Kenneth Casson Leighton
2020-05-19 17:47 ` Michael Nolan
2020-05-19 17:56 ` Luke Kenneth Casson Leighton
2020-05-19 18:01 ` [libre-riscv-dev] priority encoder replacement Jacob Lifshay
2020-05-19 18:46 ` Luke Kenneth Casson Leighton
2020-05-19 20:17 ` [libre-riscv-dev] daily kan-ban update 19may2020 Cole Poirier
2020-05-20 6:39 ` Tobias Platen
2020-05-20 11:28 ` Luke Kenneth Casson Leighton
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