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From: Hendrik Boom <hendrik@topoi.pooq.com>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
Date: Sun, 15 Mar 2020 01:10:18 -0400
Message-ID: <20200315051018.svaw4aor7ifwn725@topoi.pooq.com> (raw)
In-Reply-To: <CAC2bXD6j_Swv4iOPMGC3ZgYpc8+ThqoFnOXqpXGkk4a1e_0Nqw@mail.gmail.com>

On Sat, Mar 14, 2020 at 08:17:07PM -0700, Jacob Lifshay wrote:
> On Sat, Mar 14, 2020, 18:01 Immanuel, Yehowshua U <yimmanuel3@gatech.edu>
> wrote:
> 
> > Hello Jacob,
> >         I’m running through the numbers and studying LibreSOC’s potential
> > markets, and how we’d market the dual architecture.
> > Just how feasible is the dual architecture we’re currently embarking on.
> > Luke says its doable.
> > What are your thoughts, and what are the challenges - just trying to get a
> > comprehensive understanding.
> >
> 
> It will be quite easy to do from the hardware side due to the relative
> simplicity of user-mode RV64GC -- basically all we need is to do is
> implement the instruction decoder and clean up the odds and ends that
> result from the semantic differences.
> 
> The software side will be a little harder but still relatively easy, we
> need to implement support for translating Linux system calls from the
> RISC-V interface to the internal calls, as well as implementing the
> syscalls for switching modes between ISAs -- that's like 80% of the work on
> the Linux Kernel side. For userspace, we can have just executing RISC-V ELF
> executables as a MVP, later, we can implement the stuff in the dynamic
> linker to handle having both Power and RV code loaded in the same process
> -- I'm thinking we should use a system similar to Wine and Darling (like
> Wine but macOS on Linux) where they have two dynamic linkers in the same
> process. Will have to figure that out.

Is the multiarch feature of Linux of any use here?  I think it 
allows a choice of architecture for each *process*.  So we'd 
just have to have two sets of libraries.  We wouldn't have to link 
any code that contains both architectures.

Architecture switch would happen at system call and at process 
switch.

-- hendrik 
> 
> We can also build a bare-metal hypervisor-like program to emulate RV system
> mode to allow easier testing (don't need to boot a whole Linux kernel) as
> well as booting a whole RISC-V OS. I'd estimate that it would be less than
> 10kloc of code.
> 
> Jacob
> _______________________________________________
> libre-riscv-dev mailing list
> libre-riscv-dev@lists.libre-riscv.org
> http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev

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Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <6AC4EFD4-AA30-42C7-855A-CE68A62F107F@gatech.edu>
2020-03-15  3:17 ` Jacob Lifshay
2020-03-15  4:00   ` Luke Kenneth Casson Leighton
2020-03-15  7:59     ` Jacob Lifshay
2020-03-15 11:22       ` Luke Kenneth Casson Leighton
2020-03-15 12:09         ` [libre-riscv-dev] pearpc simulator running Luke Kenneth Casson Leighton
2020-03-15  5:10   ` Hendrik Boom [this message]
2020-03-15  6:13     ` [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility Jacob Lifshay
2020-03-15  7:18       ` Immanuel, Yehowshua U
2020-03-15 11:20         ` Luke Kenneth Casson Leighton
2020-03-15 18:19           ` Immanuel, Yehowshua U
2020-03-15 18:21             ` Immanuel, Yehowshua U
2020-03-15 18:26               ` Immanuel, Yehowshua U
2020-03-15 19:11               ` Luke Kenneth Casson Leighton
2020-03-15 19:16                 ` Immanuel, Yehowshua U
2020-03-15 19:20                   ` Immanuel, Yehowshua U
2020-03-15 19:24                     ` Luke Kenneth Casson Leighton
2020-03-15 19:25                       ` Luke Kenneth Casson Leighton
2020-03-15 19:23                   ` Luke Kenneth Casson Leighton
2020-03-15 19:32                     ` Immanuel, Yehowshua U
2020-03-15 19:43                       ` Jacob Lifshay
2020-03-15 19:52                         ` Immanuel, Yehowshua U
2020-03-15 19:57                           ` Luke Kenneth Casson Leighton
2020-03-15 20:00                             ` Immanuel, Yehowshua U
2020-03-15 20:05                               ` Luke Kenneth Casson Leighton
2020-03-15 22:04                           ` Staf Verhaegen
2020-03-15 22:10                             ` Jacob Lifshay
2020-03-15 22:23                               ` Adam Van Ymeren
2020-03-15 22:32                                 ` Luke Kenneth Casson Leighton
2020-03-16  0:25                                   ` Immanuel, Yehowshua U
2020-03-15 19:56                         ` Luke Kenneth Casson Leighton
2020-03-16  7:14                         ` Lauri Kasanen
2020-03-16  7:28                           ` Jacob Lifshay
2020-03-16  8:53                           ` Staf Verhaegen
2020-03-16  9:27                             ` Lauri Kasanen
2020-03-16 10:34                               ` Luke Kenneth Casson Leighton
2020-03-16 11:00                               ` Staf Verhaegen
2020-03-15 19:51                       ` Luke Kenneth Casson Leighton
2020-03-15 19:37                     ` Immanuel, Yehowshua U
2020-03-15 19:07             ` Luke Kenneth Casson Leighton
2020-03-15 16:57       ` Hendrik Boom

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