Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility

From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
Date: Sun, 15 Mar 2020 19:11:01 +0000
Message-ID: <CAPweEDzeLs0br0dqzxdAWCovEBA0hyxBo89SPHykr3S7nTzBFg@mail.gmail.com> (raw)
In-Reply-To: <16F24775-E25B-4E31-A1D4-145EB65FB1D8@gatech.edu>

On Sun, Mar 15, 2020 at 6:21 PM Immanuel, Yehowshua U
<yimmanuel3@gatech.edu> wrote:
>
> > I’m still not clear how keeping RISCV compatibility helps us?
> > It seems to me like excuses to keep RISCV around than an actual need to continue with it.
>
> Unless we’re breaking down POWER instructions into RISCV operations internally - which DOES make sense to me.

no it doesn't, at all.  here's the ISA tables:
https://libre-riscv.org/openpower/isatables/

those are an *internal* format (each row).

mapping to that exact same internal format by creating a RISC-V
decoder is a matter of about... 3 to 4 days work.

converting RISC-V to POWER ISA by way of a *DIRECT* conversion is an
extremely complex task, one which would normally only be considered in
software.  look at how many lines of code there are in say qemu JIT
translation and it tells you what you need to know.

l.

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