* [libre-riscv-dev] daily kan-ban update 21may2020
@ 2020-05-21 13:42 Luke Kenneth Casson Leighton
2020-05-21 13:52 ` Michael Nolan
2020-05-21 18:01 ` [libre-riscv-dev] daily kan-ban update 21may2020 Cole Poirier
0 siblings, 2 replies; 10+ messages in thread
From: Luke Kenneth Casson Leighton @ 2020-05-21 13:42 UTC (permalink / raw)
To: Libre-RISCV General Development
yesterday:
* tracking cole and michael's pipeline work. kept up with bugtracking.
* did the planned CompUnitRecord which begins a Comp Unit API
* added "register specifications" to all the pipeline Input/Output
data structures
* got annoyed at saying "no" to Jacob about a monorepo. as in: i was annoyed
*that* i had to say "no". i don't like it: i'd rather say "yes" to
at least something.
* continued a long-running discussion on comp.arch about a term that is
entirely missing from Computer Science. "Phase-aware Function Unit"
seems to cover it. took several *days* to establish.
* attended the OpenPOWER-LibreSOC bi-weekly meeting, which highlighted
a crucial fact that 3.1B UNIX Platform spec currently requires SIMD, and thus
excludes both LibreSOC and microwatt. also defined some interfaces (thanks
to Tim).
* contacted an associate who will be able to explain things to Marketnext about
the developer install dependencies.
* discussed ideas with Cole about XER and Condition Register fields.
this morni... earlier today:
* created LDSTCompUnitRecord (sorry Cesar!) derived from CompUnitRecord
* rearranged the pipeline code slightly / incrementally to create common classes
* put the "register specifications" into the pipelines, ready for auto-creating
their association with the (multiple) register files.
rest of today:
think. still trying to work out a suitable structure for how to
connect multiple (completely different) CompUnits up to regfiles.
blockers:
* DIV and MUL pipelines (Jacob)
* TRAP and SYS pipelines (Cole)
* LDSTCompUnit multi-unit testing (actually probably L0CacheBuffer
issue) (Cesar)
* L0CacheBuffer (Jacob)
l.
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* Re: [libre-riscv-dev] daily kan-ban update 21may2020
2020-05-21 13:42 [libre-riscv-dev] daily kan-ban update 21may2020 Luke Kenneth Casson Leighton
@ 2020-05-21 13:52 ` Michael Nolan
2020-05-21 15:35 ` Luke Kenneth Casson Leighton
2020-05-21 18:01 ` [libre-riscv-dev] daily kan-ban update 21may2020 Cole Poirier
1 sibling, 1 reply; 10+ messages in thread
From: Michael Nolan @ 2020-05-21 13:52 UTC (permalink / raw)
To: libre-riscv-dev
This morning I fixed the broken test_adde (it broke because I hadn't
added overflow support to caller.py). I think today I'll work on
changing the CR unit to take in the individual cr bitfields instead of
the whole CR as well as adding the necessary bits to the decoder to
handle that. If I finish that, I'll work on more formal verification.
--Michael
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* Re: [libre-riscv-dev] daily kan-ban update 21may2020
2020-05-21 13:52 ` Michael Nolan
@ 2020-05-21 15:35 ` Luke Kenneth Casson Leighton
2020-05-21 18:31 ` Tobias Platen
0 siblings, 1 reply; 10+ messages in thread
From: Luke Kenneth Casson Leighton @ 2020-05-21 15:35 UTC (permalink / raw)
To: Libre-RISCV General Development
On Thu, May 21, 2020 at 2:52 PM Michael Nolan <mtnolan2640@gmail.com> wrote:
>
> This morning I fixed the broken test_adde (it broke because I hadn't
> added overflow support to caller.py).
ohh it was in the simulation code. ok.
> I think today I'll work on
> changing the CR unit to take in the individual cr bitfields instead of
> the whole CR as well as adding the necessary bits to the decoder to
> handle that.
ok.
> If I finish that, I'll work on more formal verification.
great.
l.
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* Re: [libre-riscv-dev] daily kan-ban update 21may2020
2020-05-21 15:35 ` Luke Kenneth Casson Leighton
@ 2020-05-21 18:31 ` Tobias Platen
2020-05-21 18:51 ` Luke Kenneth Casson Leighton
0 siblings, 1 reply; 10+ messages in thread
From: Tobias Platen @ 2020-05-21 18:31 UTC (permalink / raw)
To: libre-riscv-dev
Today I was watching "Libre-SOC L0 cache/buffer walkthrough" in the morning and began looking into the scoreboard and scoremulti modules.
--
Tobias Platen <libre-soc[at]platen-software[dot]de>
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* Re: [libre-riscv-dev] daily kan-ban update 21may2020
2020-05-21 18:31 ` Tobias Platen
@ 2020-05-21 18:51 ` Luke Kenneth Casson Leighton
2020-05-21 19:09 ` Jacob Lifshay
0 siblings, 1 reply; 10+ messages in thread
From: Luke Kenneth Casson Leighton @ 2020-05-21 18:51 UTC (permalink / raw)
To: Libre-RISCV General Development
On Thu, May 21, 2020 at 7:31 PM Tobias Platen
<libre-soc@platen-software.de> wrote:
>
> Today I was watching "Libre-SOC L0 cache/buffer walkthrough" in the morning
good god, someone actually watched them :)
> and began looking into the scoreboard and scoremulti modules.
it's pretty mind-melting.
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* Re: [libre-riscv-dev] daily kan-ban update 21may2020
2020-05-21 18:51 ` Luke Kenneth Casson Leighton
@ 2020-05-21 19:09 ` Jacob Lifshay
2020-05-21 19:32 ` Luke Kenneth Casson Leighton
0 siblings, 1 reply; 10+ messages in thread
From: Jacob Lifshay @ 2020-05-21 19:09 UTC (permalink / raw)
To: Libre-RISCV General Development
Will be attending the OpenPower virtual meeting later today.
working on the mul and div units as well.
Am helping a friend build a computer, managed to accidentally get an Intel
mobo (gigabyte b365m instead of b450) and an AMD cpu, so had to send the
mobo back :(
Jacob
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* Re: [libre-riscv-dev] daily kan-ban update 21may2020
2020-05-21 19:09 ` Jacob Lifshay
@ 2020-05-21 19:32 ` Luke Kenneth Casson Leighton
2020-05-21 21:58 ` [libre-riscv-dev] openpower meeting starting shortly Jacob Lifshay
0 siblings, 1 reply; 10+ messages in thread
From: Luke Kenneth Casson Leighton @ 2020-05-21 19:32 UTC (permalink / raw)
To: Libre-RISCV General Development
On Thu, May 21, 2020 at 8:10 PM Jacob Lifshay <programmerjake@gmail.com> wrote:
>
> Will be attending the OpenPower virtual meeting later today.
oh, thank you for reminding me. anyone else welcome to attend as
well. details here:
https://openpowerfoundation.org/openpower-virtual-coffee-calls/
> working on the mul and div units as well.
great. if you like i can do a cookie-cut (stub) of the suitable
soc.fu.{siomething} code, while you do the actual pipelines in
ieee754fpu? that would give you a clear place to drop in the pipeline
stages and also i could define the regspecs?
> Am helping a friend build a computer, managed to accidentally get an Intel
> mobo (gigabyte b365m instead of b450) and an AMD cpu, so had to send the
> mobo back :(
ooo ouch. never done that, but did buy motherboards that had memory
corruption until they had a BIOS update... that was not fun, as i'd
bought *eight* of them (!)
l.
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* Re: [libre-riscv-dev] daily kan-ban update 21may2020
2020-05-21 13:42 [libre-riscv-dev] daily kan-ban update 21may2020 Luke Kenneth Casson Leighton
2020-05-21 13:52 ` Michael Nolan
@ 2020-05-21 18:01 ` Cole Poirier
2020-05-21 18:51 ` Luke Kenneth Casson Leighton
1 sibling, 1 reply; 10+ messages in thread
From: Cole Poirier @ 2020-05-21 18:01 UTC (permalink / raw)
To: Libre-RISCV General Development; +Cc: Libre-RISCV General Development
On May 21 2020, at 6:42 am, Luke Kenneth Casson Leighton <lkcl@lkcl.net> wrote:
> yesterday:
> * tracking cole and Michael's pipeline work. kept up with bugtracking.
> * discussed ideas with Cole about XER and Condition Register fields.
I just reviewed your comments on bperm TODO, I don't think this was me
but Michael, is that correct?
> blockers:
>
> * DIV and MUL pipelines (Jacob)
> * TRAP and SYS pipelines (Cole)
Again is this Michael? Or am I missing something major?
> * LDSTCompUnit multi-unit testing (actually probably L0CacheBuffer
> issue) (Cesar)
> * L0CacheBuffer (Jacob)
Yesterday I connected OP_BPERM to the fu/logical pipeline. Michael
helped me improve my code to exercise more of the... data space?
Basically he took my test, and formal proof from trivial, to
non-trivial. Today I will be working on my code with the new test bench
from Michael, and trying to get my code to pass these tests, then
modifying the formal proof accordingly.
Cole
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* Re: [libre-riscv-dev] daily kan-ban update 21may2020
2020-05-21 18:01 ` [libre-riscv-dev] daily kan-ban update 21may2020 Cole Poirier
@ 2020-05-21 18:51 ` Luke Kenneth Casson Leighton
0 siblings, 0 replies; 10+ messages in thread
From: Luke Kenneth Casson Leighton @ 2020-05-21 18:51 UTC (permalink / raw)
To: Libre-RISCV General Development
On Thu, May 21, 2020 at 7:01 PM Cole Poirier <colepoirier@gmail.com> wrote:
>
> On May 21 2020, at 6:42 am, Luke Kenneth Casson Leighton <lkcl@lkcl.net> wrote:
> > yesterday:
> > * tracking cole and Michael's pipeline work. kept up with bugtracking.
> > * discussed ideas with Cole about XER and Condition Register fields.
>
> I just reviewed your comments on bperm TODO, I don't think this was me
> but Michael, is that correct?
yes, sorry. brain-melt.
> Yesterday I connected OP_BPERM to the fu/logical pipeline. Michael
> helped me improve my code to exercise more of the... data space?
inventive and technically correct terminology. we know what you mean :)
l.
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2020-05-21 13:42 [libre-riscv-dev] daily kan-ban update 21may2020 Luke Kenneth Casson Leighton
2020-05-21 13:52 ` Michael Nolan
2020-05-21 15:35 ` Luke Kenneth Casson Leighton
2020-05-21 18:31 ` Tobias Platen
2020-05-21 18:51 ` Luke Kenneth Casson Leighton
2020-05-21 19:09 ` Jacob Lifshay
2020-05-21 19:32 ` Luke Kenneth Casson Leighton
2020-05-21 21:58 ` [libre-riscv-dev] openpower meeting starting shortly Jacob Lifshay
2020-05-21 18:01 ` [libre-riscv-dev] daily kan-ban update 21may2020 Cole Poirier
2020-05-21 18:51 ` Luke Kenneth Casson Leighton
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